Ren Zhiyuan

A 0.4V 53dB SNDR 250 MS/s time-based CT ΔΣ analog to digital converter

This paper presents the design of an ultra-low voltage (ULV), time-based, continuous-time ΔΣ analog-to-digital data converter. By replacing the 2nd stage integrator with frequency-calibrated voltage bootstrapping VCO, it circumvents ULV design challenges while achieving a signal bandwidth up to 2 MHz. Back-gate adder, voltage amplifier, and bootstrapping logic cells are also proposed to enable 250 MHz sampling rate operation. The measured peak SNDR is 53 dB under a supply voltage of 0.4 V. The whole ADC consumes 526 μW. Fabricated in a 90 nm CMOS process, the core area is 0.08 mm2.

A novel predistorter structure for memory nonlinear distortion in wideband OFDM systems

To solve the problem of memory nonlinear distortion in wideband OFDM system, a novel Frequency Domain Predistorter (FDPD) structure is proposed. The Predistorter which based on 2-dimension look-up table method is used in frequency domain. It can compensate the memory nonlinear distortion accurately, but the system performance is restricted by the size of lookup table. Then the Filter Look-Up Table (FLUT) with FDPD, which combined the FDPD with FLUT, is proposed to improve the BER performance and convergence speed. The simulation results indicate that the novel structure can decrease the BER in the receiver and increase the convergence speed.