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Dive into the research topics where Rex K. Hales is active.

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Featured researches published by Rex K. Hales.


european solid state circuits conference | 2014

Time interleaved 16 bit, 250MS/s ADC using a hybrid voltage/current mode architecture with foreground calibration

Yusuf Haque; Donald E. Lewis; Rex K. Hales; Ryan J. Kier; Tracy Johancsik; Paul T. Watkins; William Picken; Marcellus Harper; Shyam Dujari

A 16b/250 MS/s ADC employs two time-interleaved ADCs with key mismatch errors calibrated in the analog domain. The ADC achieves 73.4dB SNR and 88dBFS SFDR with a 170MHz input signal. It consumes 750mW power. Die size is 3.5mm × 3.5mm in a 0.18μm CMOS process.


Archive | 2003

Analog-to-digital converter with digital signal processing functionality to emulate many different sample frequencies, resolutions, and architectures

Rex K. Hales


Archive | 2002

Programmable architecture analog-to-digital converter

Thomas L. Wolf; David Blaine; Rex K. Hales; Marshall A. Soares


Archive | 2008

Methods and systems for calibrating a pipelined analog-to-digital converter

Donald E. Lewis; Rex K. Hales


Bulletin of The Polish Academy of Sciences-technical Sciences | 2006

Current mode sigma-delta modulator

Rex K. Hales; Kent F. Smith


Archive | 2012

Time interleaving analog-to-digital converter

Donald E. Lewis; Ryan J. Kier; Rex K. Hales; Yusuf Haque


Archive | 2013

RANDOMIZED TIME-INTERLEAVED SAMPLE-AND-HOLD SYSTEM

Donald E. Lewis; Ryan J. Kier; Rex K. Hales; Yusuf Haque


Archive | 2007

SENSING LIGHT AND SENSING THE STATE OF A MEMORY CELL

Rex K. Hales; Tracy Johancsik; Thomas L. Wolf


Archive | 2012

PIPELINED ADC STAGE FILTERS

Yusuf Haque; Ryan J. Kier; Rex K. Hales; Paul T. Watkins; Marcellus Harper


Archive | 2007

Current Mode Pipelined Analog-to-Digital Converter

Thomas L. Wolf; Rex K. Hales

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Thomas L. Wolf

Charles Stark Draper Laboratory

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Tracy Johancsik

Charles Stark Draper Laboratory

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Donald E. Lewis

Charles Stark Draper Laboratory

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Kent F. Smith

Charles Stark Draper Laboratory

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