Reza Lotfi

Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation results in a 0.18- μm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 2.5 and 1.1 GHz at supply voltages of 1.2 and 0.6 V, while consuming 1.4 mW and 153 μW, respectively. The standard deviation of the input-referred offset is 7.8 mV at 1.2 V supply.

Analysis of Power Consumption and Linearity in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs

Successive-approximation analog-to-digital converters (SA-ADCs) are widely used in ultra-low-power applications. In this paper, the power consumption and the linearity of capacitive-array digital-to-analog converters (DACs) employed in SA-ADCs are analyzed. Specifically, closed-form formulas for the power consumption as well as the standard deviation of INL and DNL for three commonly-used radix-2 architectures including the effect of parasitic capacitances are presented and the structures are compared. The proposed analysis can be employed in choosing the best architecture and optimizing it in both hand calculations and computer-aided-design tools. Measurement results of previously published works as well as simulation results of a 10-bit 10 kS/s SA-ADC confirm the accuracy of the proposed equations. It will be shown that, in spite of what commonly is assumed, although the total capacitance and the power consumption of those architectures employing attenuating capacitors seem to be smaller than conventional binary-weighted structures, the linearity requirements impose much larger unit capacitance to the structure such that the entire power consumption is larger.

A Level-Crossing Based QRS-Detection Algorithm for Wearable ECG Sensors

In this paper, an asynchronous analog-to-information conversion system is introduced for measuring the RR intervals of the electrocardiogram (ECG) signals. The system contains a modified level-crossing analog-to-digital converter and a novel algorithm for detecting the R-peaks from the level-crossing sampled data in a compressed volume of data. Simulated with MIT-BIH Arrhythmia Database, the proposed system delivers an average detection accuracy of 98.3%, a sensitivity of 98.89%, and a positive prediction of 99.4%. Synthesized in 0.13 μm CMOS technology with a 1.2 V supply voltage, the overall system consumes 622 nW with core area of 0.136 mm2 which make it suitable for wearable wireless ECG sensors in body-sensor networks.

Design optimization of analog integrated circuits using simulation-based genetic algorithm

One of the most important facilities required in the synthesis of an advanced mixed-mode system is the efficient and if possible automated analog design tool. In this paper an accurate method to determine the device sizes in an analog integrated circuit on the basis of genetic algorithm (GA) is presented. In order to evaluate the fitness of the circuit specifications in any iteration of the GA, HSPICE simulation is used. Examples in both time and frequency domains for an operational transconductance amplifier are presented. The simulation results confirm the efficiency of GA in determining the device sizes in an analog circuit.

A Low-Power Subthreshold to Above-Threshold Voltage Level Shifter

This brief presents a power-efficient voltage level-shifter architecture that is capable of converting extremely low levels of input voltages to higher levels. In order to avoid the static power dissipation, the proposed structure uses a current generator that turns on only during the transition times, in which the logic level of the input signal is not corresponding to the output logic level. Moreover, the strength of the pull-up device is decreased when the pull-down device is pulling down the output node in order for the circuit to be functional even for the input voltage lower than the threshold voltage of a MOSFET. The operation of the proposed structure is also analytically investigated. Post-layout simulation results of the proposed structure in a 0.18-μm CMOS technology show that at the input low supply voltage of 0.4 V and the high supply voltage of 1.8 V, the level shifter has a propagation delay of 30 ns, a static power dissipation of 130 pW, and an energy per transition of 327 fJ for a 1-MHz input signal.

An ultra-low-power 10-Bit 100-kS/s successive-approximation analog-to-digital converter

Successive-approximation analog-to-digital converters (SA-ADCs) have recently been widely used for moderate-speed moderate-resolution applications where power consumption is of major concern. In this paper, several techniques are proposed to further reduce the power consumption of an SA-ADC. These solutions include a splitsegmented architecture for the capacitor-based digital-to-analog converter (DAC), a modified switching scheme for the DAC, and employing a smaller supply voltage for the comparator and the successive-approximation register while using a new powerefficient digital level converter. Spectre simulation results of a single-ended 10-bit 100kS/s SA-ADC in a 0.13-µm CMOS technology employing the proposed techniques show that the ADC (excluding reference buffers) consumes less than 1 µW of power while offering an effective number of bits of 9.2.

Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications

Power consumption is one of the main design challenges in very-low-voltage high-speed analog integrated circuits. In this paper, different techniques to reduce the power consumption in low-voltage fast-settling operational amplifiers for switched-capacitor applications are discussed. These techniques include the cascode compensation, a new class-A/AB output stage and a novel dynamic allocation of settling time parameters. Design considerations for a 1.5-V very-low-power operational amplifier merging these techniques are addressed. HSPICE simulation results of the circuit in a 0.25-µm CMOS process confirm the effectiveness of the approaches to considerably reduce the power consumption of high-speed operational amplifiers.

Ultra-Low-Voltage, Low-Power, High-Speed Operational Amplifiers Using Body-Driven Gain-Boosting Technique

Regular gate-driven regulated-cascode structure fails to operate with very-low supply voltages. On the other hand, body-driven configuration suffers from limited speed due to limited effective transconductance. In this letter, body-driven gain-boosting amplifier has been employed for a regular gate-driven folded-cascode amplifier to enhance its voltage gain without any limitation on its minimum required supply voltage and voltage swing in ultra-low-voltage applications. The gain/speed/swing performance of the proposed low-voltage op-amp would be therefore good enough not to require another amplifying stage in many high-speed low-power applications. Using the proposed architecture, three different sub-l-V single-stage operational amplifiers have been designed and simulated in 0.18-mum CMOS technology that confirm the suitable operation of the circuit in very-low supply voltages and different speeds.

A low-power design methodology for high-resolution pipelined analog-to-digital converters

In this paper a general method to design a pipelined ADC with minimum power consumption is presented. By expressing the total static power consumption and the total input-referred noise of the converter as functions of the capacitor values and the resolutions of the converter stages, a simple optimization algorithm is employed to calculate the optimum values of these parameters, which lead to minimum power consumption while a specified noise requirement is satisfied. To determine the bias current values of operational amplifiers, a novel optimal choice for settling and slewing time parameters is proposed applicable to both single-stage and two-stage Miller-compensated opamp structures. Using the proposed methodology, the optimum values for capacitors, the resolutions and the opamp device sizes of all stages are determined in order to minimize the total power consumption. Design examples are presented and compared with conventional approaches to show the effectiveness of the proposed methodology.

Design of high-speed two-stage cascode-compensated operational amplifiers based on settling time and open-loop parameters

Settling behavior of operational amplifiers is of great importance in many applications. In this paper, an efficient methodology for the design of high-speed two-stage operational amplifiers based on settling time is proposed. Concerning the application of the operational amplifier, it specifies proper open-loop circuit parameters to obtain the desired settling time and closed-loop stability. As the effect of transfer function zeros has been taken into account, the proposed methodology becomes more accurate in achieving the desired specifications. Simulation results are presented to show the effectiveness of the methodology.