Hassan Sepehrian

A signal-specific successive-approximation analog-to-digital converter

This paper presents a modified structure and a new switching algorithm in successive-approximation analog-to-digital converters to reduce the power consumption. This technique is more efficient in applications where the input signal activity is low most of the time such as biomedical signals. For slow-varying samples, only the least significant bits of the new analog sample are extracted leading to power saving in both the capacitor-based DAC and the comparator. For an Electrocardiogram signal and with the proposed structure, the simulated power consumption of the DAC, the comparator and the entire ADC for an 8-bit 1-kS/s converter are 75%, 43% and 50% smaller than those of a conventional architecture, respectively.

Time-Domain Large-Signal Modeling of Traveling-Wave Modulators on SOI

Silicon photonic modulators have strong nonlinear behavior in phase modulation and frequency response, which needs to be carefully addressed when they are used in high-capacity transmission systems. We demonstrate a comprehensive model for depletion-mode Mach-Zehnder modulators (MZMs) on silicon-on-insulator, which provides a bridge between device design and system performance optimization. Our methodology involves physical models of p-n-junction phase-shifters and traveling-wave electrodes, as well as circuit models for the dynamic microwave-light interactions and time-domain analysis. Critical aspects in the transmission line design for high-frequency operation are numerically studied for a case of p-n-junction loaded coplanar-strip electrode. The dynamic interaction between light and microwave is simulated using a distributed circuit model solved by the finite-difference time-domain method, allowing for accurate prediction of both small-signal and large-signal responses. The validity of the model is confirmed by the comparison with experimental results for a series push-pull MZM with a 6 mm phase shifter. The simulation shows excellent agreement with experiment for high-speed operation up to 46 Gb/s. We show that this time-domain model can well predict the impact of the nonlinear behavior on the large-signal response, in contrast to the poor prediction from linear models in the frequency domain.

A low-power current-reuse analog front-end for multi-channel neural signal recording

Studying brain activity in-vivo requires to simultaneously record bioelectrical from several microelectrodes in order to capture neurons interactions. In this work, we present a new current-reuse analog front-end (AFE), which is scalable to very large number of recording channels, thanks to its small implementation area and its low-power consumption. This proposed AFE includes a low-noise amplifier (LNA) and a programmable gain amplifier (PGA) which employ fully differential folded cascode current-reuse structures leading to decreased power consumption and silicon area. Moreover, the proposed AFE presents improved output swing compared to previous current-reuse topologies by employing different common mode feedback circuits for LNA and PGA. A 4-channel system implemented in a CMOS 0.18-μm technology is presented as a proof-of-concept. Post-layout simulation results are reported to verify its performance. The total power consumption of one channel including a low-noise amplifier and a variable gain stage is 8.2 μW (4.1 μw for LNA and 4.1 μw for PGA), for an input referred noise of 3.28 μV. The entire AFE presents four selectable gains of 45.2 dB, 50.1 dB, 55.3 dB and 59.65 dB, and occupies a die area of 0.035 mm2 per channel.

CMOS-Photonics Codesign of an Integrated DAC-Less PAM-4 Silicon Photonic Transmitter

Codesign and integration of optical modulators and CMOS drivers is crucial for high-speed silicon photonic (SiP) transmitters to reach their full potential for low-cost, low-power electronic-photonic integrated systems. We present a CMOS-driven SiP multi-level optical transmitter implemented using a commercially available lateral p-n junction process. It uses a Mach-Zehnder modulator (MZM) segmented to increase speed and to lower the required power on a per segment basis to a level achievable with CMOS. A multi-channel driver is designed and implemented in 130 nm RF CMOS, providing a swing of 4 V in a push-pull configuration at 20 Gbaud. Binary data at the CMOS input is manipulated via digital logic to produce the proper per-segment drive signals to generate a four-level pulse-amplitude modulation optical signal. Multi-level modulation is achieved using only binary signals as input (DAC-less). Cosimulation of the optical and electrical circuits shows good agreement with experiment. Reliable transmission is achieved without post-compensation at 28 Gb/s, and at 38 Gb/s when using post-compensation.

Flexible on-chip frequency comb generation using a SOI dual-drive MZM

We demonstrate comb generation on 220-nm silicon-on-insulator, enabled by a dual-drive Mach-Zehnder modulator, by which 7 comb lines with 7dB flatness and 5 lines with 3dB flatness have been achieved. This provides a promising solution for flexible multicarrier transmitters on silicon.

Multi-stage 20 Gbaud driver in 130 nm CMOS for segmented Mach-Zehnder optical modulators

High speed silicon optical modulators must be compatible with CMOS drivers to reach their full potential for low cost and low power consumption. We designed a CMOS driver for a Mach-Zehnder modulator (MZM) that has been segmented to lower required voltage swings on a per segment basis and to increase the speed. Previous inductor-less drivers produced on the same process, IBM 130 nm CMOS, ran at 10 Gb/s for on-off keying driving a traveling wave (not segmented) MZM. Our chip runs at 20 Gb/s input and performing logic on two data inputs to drive multiple segments to achieve PAM4 modulation, therefore enabling 40 Gb/s operation. The chip provides three drive signals, one for each segment of the MZM. Our measurements verify that at 20 Gb/s the driver provides 2V peak-to-peak voltage swing (4V p-p voltage swing in a push-pull configuration) over a 50Ω load.

A low-power current-reuse dual-band analog front-end for multi-channel neural signal recording.

Thoroughly studying the brain activity of freely moving subjects requires miniature data acquisition systems to measure and wirelessly transmit neural signals in real time. In this application, it is mandatory to simultaneously record the bioelectrical activity of a large number of neurons to gain a better knowledge of brain functions. However, due to limitations in transferring the entire raw data to a remote base station, employing dedicated data reduction techniques to extract the relevant part of neural signals is critical to decrease the amount of data to transfer. In this work, we present a new dual-band neural amplifier to separate the neuronal spike signals (SPK) and the local field potential (LFP) simultaneously in the analog domain, immediately after the pre-amplification stage. By separating these two bands right after the pre-amplification stage, it is possible to process LFP and SPK separately. As a result, the required dynamic range of the entire channel, which is determined by the signal-to-noise ratio of the SPK signal of larger bandwidth, can be relaxed. In this design, a new current-reuse low-power low-noise amplifier and a new dual-band filter that separates SPK and LFP while saving capacitors and pseudo resistors. A four-channel dual-band (SPK, LFP) analog front-end capable of simultaneously separating SPK and LFP is implemented in a TSMC 0.18 μm technology. Simulation results present a total power consumption per channel of 3.1 μw for an input referred noise of 3.28 μV and a NEF for 2.07. The cutoff frequency of the LFP band is fc=280 Hz, and fL=725 Hz and fL=11.2 KHz for SPK, with 36 dB gain for LFP band 46 dB gain for SPK band.

A new scheme of coupling VCOs for the purpose of injection locking frequency divider

The coupling of oscillators is reviewed. A new scheme of coupling of VCOs is proposed in which no extra elements are needed to couple the VCOs, which leads to a lower phase noise and power consumption. Based on simulation results, a lock-in range from 15.7 GHz to 18.7 GHz for a divide-by-3, and from 16.4 GHz to 17 GHz for a divide-by-5 were achieved with a 180 nm CMOS technology with a Vdd=1.8 V.

A low-power Successive Approximation ADC for biomedical applications

A new switching algorithm is proposed in Successive Approximation Analog-to-Digital Converters (SA-ADCs) to reduce the power consumption in both DAC and comparator. This technique is more efficient in applications where the input signal has low-varying characteristics. For slow-varying samples, only the least significant bits of the new analog sample are extracted leading to power saving in both the capacitor-based DAC and the comparator. For an Electrocardiogram (ECG) signal and with the proposed structure, the simulated power consumption of the DAC, the comparator and the entire ADC for an 8-bit 10-kS/s converter are 74%, 38% and 52% less than those of a conventional architecture, respectively.

A CMOS Synthesizer using a new scheme of injection locking of VCOs

A new method of coupling oscillators is used for the purpose of frequency synthesis. The new method has the advantages of wider locking range, adding fewer sources of noise and lower power consumption compared to the older methods.