Ricardo Andres Aroca

A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link

This paper presents a directly modulated, 60 GHz zero-IF transceiver architecture suitable for single-carrier, low-power, multi-gigabit wireless links in nanoscale CMOS technologies. This mm-wave front end architecture requires no upconversion of the baseband signals in the transmitter and no analog-to-digital conversion in the receiver, thus minimizing system complexity and power consumption. All circuit blocks are realized using sub-1.0 V topologies, that feature only a single high-frequency transistor between the supply and ground, and which are scalable to future 45 nm, 32 nm, and 22 nm CMOS nodes. The transceiver is fabricated in a 65 nm CMOS process with a digital back-end. It includes a receiver with 14.7 dB gain and 5.6 dB noise figure, a 60 GHz LO distribution tree, a 69 GHz static frequency divider, and a direct BPSK modulator operating over the 55-65 GHz band at data rates exceeding 6 Gb/s. With both the transmitter and the receiver turned on, the chip consumes 374 mW from 1.2 V which reduces to 232 mW for a 1.0 V supply. It occupies 1.28 times 0.81 mm2. The transceiver and its building blocks were characterized over temperature up to 85^deg C and for power supplies down to 1 V. A manufacturability study of 60 GHz radio circuits is presented with measurements of transistors, the low-noise amplifier, and the receiver on slow, typical, and fast process splits. The transceiver architecture and performance were validated in a 1-6 Gb/s 2-meter wireless transmit-receive link over the 55-64 GHz range.

A 95GHz Receiver with Fundamental-Frequency VCO and Static Frequency Divider in 65nm Digital CMOS

This paper presents a fully integrated receiver, with LNA, mixer, IF amplifier, fundamental-frequency quadrature VCO, and static frequency divider, operating at 95GHz in a 65nm general-purpose (GP) CMOS technology. The receiver consumes 206mW from a 1.2V/1.5V supply. With large RF and IF bandwidths of over 19GHz and 16GHz, respectively, it is suitable for passive-imaging applications, and for wireless chip-to-chip communication at data-rates exceeding 20Gb/s. Together with the recently reported 60GHz receiver in 90nm CMOS, this 95GHz receiver in 65nm CMOS demonstrates that scaling of entire mm-wave receivers is possible in both frequency coverage and across technology nodes.

Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS

This paper presents low-voltage circuit topologies for 40-Gb/s communications in 90-nm and 65-nm CMOS. A retiming flip-flop implemented in two different 90-nm CMOS technologies employs a MOS-CML Master-Slave latch topology with only two vertically stacked transistors. Operation at 40 Gb/s is achieved by a combination of low and high-VT MOSFETs in the latch. Full-rate retiming with jitter reduction is demonstrated up to 40 Gb/s. Low-power broadband amplifiers based on resistor-inductor transimpedance feedback are realized in 90-nm and 65-nm CMOS to investigate the portability of high-speed building blocks between technology nodes. Experiments show that the transimpedance amplifier based on the CMOS inverter can reach 40-Gb/s operation with a record power consumption of 0.15 mW/Gb/s. A comparison between CMOS technologies underlines the importance of General Purpose rather than Low Power processes for high-speed digital design.

A zero-IF 60GHz transceiver in 65nm CMOS with ≫ 3.5Gb/s links

This paper presents a 1.2 V 60 GHz zero-IF transceiver fabricated in a 65 nm CMOS process with a digital back-end. The chip includes a receiver with 14.7 dB gain, a low 5.6 dB noise figure, a 60 GHz LO distribution tree, a 64 GHz static frequency divider, and a direct BPSK modulator operating over the 55-65 GHz band at data rates exceeding 3.5 Gb/s. The chip consumes 374 mW (232 mW) from 1.2 V (1.0 V) and occupies 1.28 times 0.81 mm2. The transceiver was characterized over temperature up to 85degC and for power supplies down to 1 V. A manufacturability study of 60 GHz radio circuits is presented with measurements of transistors, the low-noise amplifier, and the receiver on typical and fast process splits. The transceiver performance is demonstrated using a 3.5 Gb/s 2-meter wireless transmit-receive link over the 55-64 GHz range.

A Large Swing, 40-Gb/s SiGe BiCMOS Driver With Adjustable Pre-Emphasis for Data Transmission Over 75

A fully differential 40-Gb/s cable driver with adjustable pre-emphasis is presented. The circuit is fabricated in a production 0.18 mum SiGe BiCMOS technology. A distributed limiting architecture is used for the driver employing high-speed HBTs in the lower voltage predriver, and a high-breakdown MOS-HV-HBT cascode, consisting of a 0.18 mum n-channel MOSFET and a high-voltage HBT (HV-HBT), for the high voltage output stages. The circuit delivers up to 3.6 V peak-to-peak per side into a 75 Omega load with variable pre-emphasis ranging from 0 to 400%. S-parameter measurements show 42 dB differential small-signal gain, a 3-dB bandwidth of 22 GHz, gain peaking control up to 25 dB at 20 GHz and input and output reflection coefficients better than -10 dB up to 40 GHz. Additional features of the driver include output amplitude control (from 1 Vpp to 3.6 Vpp per side), pulse-width control (35% to 65%) and an adjustable input dc level (1.1 V to 1.8 V) allowing the circuit to interface with a SiGe BiCMOS or MOS-CML SERDES. The transmitter is able to generate an eye opening at 38 Gb/s after 10 m of Belden 1694 A coaxial cable which introduces 22 dB of loss at 19 GHz. Measurement results also demonstrate that the transmitter IC operates as a standalone equalizer for 10-Gb/s data transmission over 40 m of Belden cable without the need for receiver equalization.

\Omega

This paper describes first a half-rate, 2.5-V, 1.4-W, 87-Gb/s transmitter with on-chip PLL fabricated in a production 130-nm SiGe BiCMOS process. Next, the most critical blocks required for the implementation of a full-rate 100-Gb/s serial transceiver are explored. State-of-the art 105-GHz, SiGe HBT static frequency dividers and VCOs operating from 2.5-V supply, as well as 65-nm CMOS, 1.2-V, 90-GHz static frequency dividers, low-phase noise VCOs, and 100-GHz clock distribution network amplifiers are fully characterized over power supply and process spread, and over temperature up to 100degC. Inductor and transformer modeling and scaling beyond 200 GHz in nanoscale CMOS and SiGe BiCMOS technologies, are also described.

Coaxial Cable

The first 50-GHz to 110-GHz downconverter in 45-nm digital CMOS is presented along with the mm-wave characterization of AMOS varactors, inductors and transformers. The varactor Q is higher than 6, up to 94 GHz. The downconverter gain is 15 dB at 111GHz, and is employed as a broadband test vehicle to characterize the optimal noise figure current density (JOPT) of 45-nm MOSFETs in the 50 GHz to 110 GHz range.

Towards a sub-2.5V, 100-Gb/s Serial Transceiver

The design of a 60-Gb/s CMOS driver with input signal retiming is analyzed theoretically and validated experimentally. The output stage employs a modified distributed amplifier (DA) architecture with summation of both low-pass and reactively coupled bandpass signal paths along a 50-Ω output transmission line. The DA features digital variable gain amplifier (DVGA) cells to achieve broadband waveshape control with adjustable pre-emphasis at three different peaking frequencies. Binary-weighted MOSFET gate-finger groupings are employed in a Gilbert-cell based DVGA topology to minimize bit-dependent output impedance and group delay variations. S -parameter measurements of the retimed driver show 54-dB gain, while the standalone DA exhibits approximately 10 dB of peaking control in each of the three frequency bands. Input and output return loss is better than -10 dB up to 60 GHz. The circuit operates from 1.2- and 2-V supplies and achieves a throughput efficiency of 12.2 mW/Gb/s. Equalization experiments at 40 Gb/s demonstrate compensation of various channel characteristics, including over 12 feet of cascaded coaxial cables with 21 dB loss at 20 GHz.

Circuit performance characterization of digital 45-nm CMOS technology for applications around 110 GHz

This paper presents circuit design methodologies, modeling techniques, and circuit architectures for silicon transceivers above 77 GHz. The architectures of three existing CMOS and SiGe BiCMOS receivers and transceivers are compared to demonstrate the variety of choices available to the circuit designer, and to highlight design challenges that arise in transceivers above 77 GHz. A comparison of 65 nm CMOS and 130 nm SiGe BiCMOS circuits illustrates the suitability of both technologies in W-Band systems. Inductor and transformer scaling is demonstrated beyond 160 GHz, and the extension of an existing modeling technique for inductors is shown to accurately model transformers and transmission lines. The optimum biasing of power amplifiers is investigated in CMOS and SiGe HBT technologies.

A 2.4-

A 60-Gb/s CMOS driver employing mm-wave DACs to achieve broadband waveshape control and pre-emphasis at different peaking frequencies is presented. It features a modified distributed amplifier (DA) architecture that achieves low-voltage and high- speed summation of both low-pass and reactively- coupled bandpass signal paths along an output transmission line. Using binary-weighted MOSFET gate fingers in Gilbert-cell based DACs, the circuit can supply variable output swing up to 1.2V peak-to-peak per side in a 50Ω load and independent digital pre- emphasis control at 25 GHz, 35 GHz and 45 GHz, respectively. S-parameter measurements of the entire retimed transmitter show 60dB of differential gain, while the standalone DA exhibits approximately 10 dB of peaking control in each of the three frequency bands. Input and output return loss is better than - 10 dB up to 60 GHz. The entire circuit, including the transimpedance-limiting-amplifier-retimer, operates from 1.2V and 2V supplies and achieves a throughput efficiency of 12.2 mW/Gb/s.