Peter Schvan

Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio

Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor fT/fMAX of 120 GHz/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB bandwidth >13 GHz, a P 1dB of +6.4 dBm with 7% PAE and a saturated output power of +9.3 dBm at 60 GHz. The LNA represents the first 90-nm CMOS implementation at 60 GHz and demonstrates improvements in noise, gain and power dissipation compared to earlier 60-GHz LNAs in 160-GHz SiGe HBT and 0.13-mum CMOS technologies. It features 14.6 dB gain, an IIP 3 of -6.8 dBm, and a noise figure lower than 5.5 dB, while drawing 16 mA from a 1.5-V supply. The use of spiral inductors for on-chip matching results in highly compact layouts, with the total PA and LNA die areas with pads measuring 0.35times0.43 mm2 and 0.35times0.40 mm2, respectively

A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design

Fully scalable, analytical HF noise parameter equations for bipolar transistors are presented and experimentally tested on high-speed Si and SiGe technologies. A technique for extracting the complete set of transistor noise parameters from Y parameter measurements only is developed and verified. Finally, the noise equations are coupled with scalable variants of the HICUM and SPICE-Gummel-Poon models and are employed in the design of tuned low noise amplifiers (LNAs) in the 1.9-, 2.4-,and 5.8-GHz bands.

A 24GS/s 6b ADC in 90nm CMOS

This paper presents a 24 GS/s 6 b ADC in 90 nm CMOS with the highest ENOB up to 12 GHz input frequency and lowest power consumption of 1.2 W compared to ADCs with similar performance. It uses an interleaved architecture of SAR type self-calibrating converters operating from 1 V supply combined with an array of 2.5 V T/Hs with delay, gain and offset-calibration capability.

A 40GS/s 6b ADC in 65nm CMOS

Progress in 40Gb/s optical dual- polarization (DP) QPSK systems inspired an idea of 100G transmission by optical frequency division multiplexing (FDM) of QPSK-modulated channels [1]. A practical solution suggests two 58Gb/s DP QPSK channels, spaced by 50GHz (Fig. 21.7.1). The challenge is in implementing a 6b ADC operating at sampling rate of 29Gs/s, as compared to 24Gs/s reported before [2]. The other challenge is reduction of ADC sampling jitter. In an interleaved architecture, jitter is limited by the timing mismatch between the clocks of T&H circuits. While initial timing error is compensated during ADC calibration, its spread over the input frequency range and drift may still impact jitter performance. This paper presents, to our knowledge for the first time, a 6b ADC operating up to 40Gs/s with power dissipation ≪ 1.5W. The 30% margin for the sampling rate reduces interleaved timing errors and therefore sampling jitter below 0.25ps-rms. The ADC also includes on-chip test signal synthesizer that generates a gigahertz range sinusoidal signal to simplify production testing.

A 22GS/s 6b DAC with integrated digital ramp generator

A 22GS/s 6b DAC is presented that includes a digital ramp pattern generator. The DAC core and ramp generator consume 2W and 1.2W respectively operating from 3.3V. The DAC produces a differential signal up to 1.3V/sub pp/ DNL<0.5LSB and INL<0.9LSB are measured. The highest glitch energy is 0.5pVs. Settling times are 70 and 40ps for full- and half-scale transitions, respectively.

Frequency Scaling and Topology Comparison of Millimeter-wave CMOS VCOs

This paper presents an algorithmic design methodology and frequency scaling technique for CMOS VCOs. It illustrates the almost ideal scaling of a fundamental 10-GHz, 90-nm CMOS Colpitts VCO with -117 dBc/Hz phase noise and 4 dBm output power to 77 GHz. The 77-GHz VCO features linear 8.3% tuning range and a phase noise of -100.3 dBc/Hz at 1 MHz offset. The first complementary cross-coupled VCO operating at 77 GHz is also reported. In addition, a new figure of merit for CMOS VCO based on the one defined in the 2003 ITRS is proposed to adequately account for the VCO output power and efficiency

A scalable high frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design

Fully scalable, analytical HF noise parameter equations for bipolar transistors are presented and experimentally tested on high speed Si and SiGe technologies. A technique for extracting the complete set of transistor noise parameters from Y parameter measurements only is developed and verified. Finally, the usefulness of the noise model is demonstrated in the design of tuned LNAs in the 1.9 GHz, 2.4 GHz, and 5.8 GHz bands.

A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBT limiting amplifier

This limiting amplifier IC is implemented in a silicon-germanium (SiGe) HBT technology for low-cost 10 Gb/s fibre-optic applications. The IC employs 20 dB gain limiting cells, input overload protection, split analog/digital grounds and on-chip isolation interface with transmission lines. Sensitivity is 3.5 mV/sub pp/ at 10/sup -9/ BER with 2 V/sub pp/ maximum input and differential output. The gain is over 60 dB and S/sub 21/ bandwidth exceeds 15 GHz at 10 mVpp input. AM to PM conversion is less than 5 ps across a three-decade range of input amplitude.

CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples

This paper investigates the suitability of 90nm and 65nm GP and LP CMOS technology for SOC applications in the 60GHz to 100GHz range. Examples of system architectures and transceiver building blocks are provided which emphasize the need for aggressively scaled GP CMOS and low-VT transistors if CMOS is to compete with SiGe BiCMOS above 60 GHz. This requirement is in conflict with the 2005-ITRS proposal to use LP CMOS for RF applications.

A low-voltage silicon bipolar RF front-end for PCN receiver applications

Monolithic microstrip transformers are used to perform the coupling and phase-splitting functions in a bipolar low-noise amplifier and mixer designed for 1.9GHz wireless receiver applications. These circuits are fabricated in a production 0.8/spl mu/m BiCMOS process with a transistor transit frequency of 11GHz. Using reactive feedback and coupling elements in place of resistors significantly improves the noise figure through the reduction of resistor thermal noise, and also allows both the low-noise amplifier and the mixer to operate at supply voltages below 2V.