Riccardo Mariani

Fault-robust microcontrollers for automotive applications

The design space that a system architect should manage when designing a microcontroller for a safety related system is rather large due to the variety of faults that can affect the given equipment under control (EUC), the different failures that these faults can generate and the wide set of techniques that can be used to detect, confine or stop the resulting hazards, each one with its efficiency and cost. In this paper it is proposed a systematic platform-based approach, in which a library of blocks (HW and SW) is used together with a set of tools and methodologies to find the optimum solution in this design space, following the IEC61508 guidelines

Towards improved survivability in safety-critical systems

Performance demand of Critical Real-Time Embedded (CRTE) systems implementing safety-related system features grows at an exponential rate. Only modern semiconductor technologies can satisfy CRTE systems performance needs efficiently. However, those technologies lead to high failure rates, thus lowering survivability of chips to unacceptable levels for CRTE systems. This paper presents SESACS architecture (Surviving Errors in SAfety-Critical Systems), a paradigm shift in the design of CRTE systems. SESACS is a new system design methodology consisting of three main components: (i) a multicore hardware/firmware platform capable of detecting and diagnosing hardware faults of any type with minimal impact on the worst-case execution time (WCET), recovering quickly from errors, and properly reconfiguring the system so that the resulting system exhibits a predictable and analyzable degradation in WCET; (ii) a set of analysis methods and tools to prove the timing correctness of the reconfigured system; and (iii) a white-box methodology and tools to prove the functional safety of the system and compliance with industry standards. This new design paradigm will deliver huge benefits to the embedded systems industry for several decades by enabling the use of more cost-effective multicore hardware platforms built on top of modern semiconductor technologies, thereby enabling higher performance, and reducing weight and power dissipation. This new paradigm will further extend the life of embedded systems, therefore, reducing warranty and early replacement costs.

A Functional Verification based Fault Injection Environment

Fault injection is needed for different purposes such as analyzing the reaction of a system in a faulty environment or validating fault-detection and/or fault-correction techniques. In this paper we propose a simulation-based fault injection tool able to work at different abstraction levels and with user-defined fault models. By exploiting the facilities provided by a functional verification environment it allows to speed up the entire fault injection process: from the creation of the workload to the analysis of the results of injection campaigns. Moreover, the adoption of techniques to optimize the fault list significantly reduces the simulation time. Being the tool targeted to the validation of dependable systems, it includes a way to extract information from the Failure Mode and Effect Analysis and to correlate fault injection results with estimates.

Comparing fail-safe microcontroller architectures in light of IEC 61508

In this paper, an overview is given on the main architectures used in the automotive to implement fail-safe microcontrollers. The concept of a new HW-centric, distributed and optimized architecture is also presented. In light of the IEC 61508 norm for safety related electronic systems, a comparisons between these different architectures is done based on a reference design. The paper concludes discussing how the presented architectures can be extended to become fail-functional

Scrubbing and partitioning for protection of memory systems

Based on the definition of a mission vulnerability factor, this paper proposes the use of on-line memory scrubbing technique joined with memory partitioning, describing how such approach can help to reduce overhead and performance penalties of ECC-based protection systems.

Towards functional-safe timing-dependable real-time architectures

In the near future the automotive systems will include microcontrollers hosting homogeneous or heterogeneous multi-core architectures, in which two or more CPU cores are combined to satisfy the high performance requirements. For those devices, time dependability issues represent a key challenge. In addition to that, they shall satisfy standards like ISO 26262 for functional safety and AUTOSAR for software architectures. This paper focuses on the study of problems and solutions related to functional-safe timing-dependable real-time architectures; in particular we identify critical failures related to timing issues and we propose a functional-safety aware methodology combining HW and SW measures to handle such kind of failures.

On-Line Instruction-Checking in Pipelined Microprocessors

Microprocessors performances have increased by more than five orders of magnitude in the last three decades. As technology scales down, these components become inherently unreliable posing major design and test challenges. This paper proposes an instruction-checking architecture to detect erroneous instruction executions caused by both permanent and transient errors in the internal logic of a microprocessor. Monitoring the correct activation sequence of a set of predefined microprocessor control/status signals allow distinguishing between correctly and not correctly executed instructions.

Cross-Layer Early Reliability Evaluation for the Computing cOntinuum

Advanced multifunctional computing systems realized in forthcoming technologies hold the promise of a significant increase of the computational capability that will offer end-users ever improving services and functionalities (e.g., next generation mobile devices, cloud services, etc.). However, the same path that is leading technologies toward these remarkable achievements is also making electronic devices increasingly unreliable, posing a threat to our society that is depending on the ICT in every aspect of human activities. Reliability of electronic systems is therefore a key challenge for the whole ICT technology and must be guaranteed without penalizing or slowing down the characteristics of the final products. CLERECO EU FP7 (GA No. 611404) research project addresses early accurate reliability evaluation and efficient exploitation of reliability at different design phases, since these aspects are two of the most important and challenging tasks toward this goal.

RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU

Reliability1assessment has always been a major concern in the design of computing systems. The results of the assessment highlight and guide enhancements which trigger redesign cycles; thus early and accurate reliability assessment is of profound importance. For the purposes of early reliability analysis, abstract models of the design (which are available in early design stages) are typically used. These models, however, may not be completely accurate compared to the actual final design. Existing literature has not quantified this inaccuracy, through a comparison between Register-Transfer-Level (RTL) and microarchitecture-level reliability assessment on the same commercial microprocessor design. In this paper, we perform reliability assessment using statistical fault-injection on the RTL and Microarchitectural models of the same commercial ARM® Cortex®-A9 processor. The assessment was performed using the same benchmark workloads and equivalent configurations of the hardware structures. The results show that, compared to RTL model, the almost 200x faster microarchitectural model reports an average difference of 0.7 percentile units (10%) on the vulnerability estimation of register file and 3 percentile units (20%) on the vulnerability estimation of L1 data cache.

Cross-layer early reliability evaluation: Challenges and promises

Evaluation of computing systems reliability must be accurate enough to provide hints for the required fault protection mechanisms that will guarantee correctness of operation at acceptance costs. To be useful, reliability evaluation must be performed early enough in the design cycle when, however, the available details of the system are largely unknown. This inherent contradiction in terms: early vs. accurate, requires a cross-layer approach for reliability evaluation. Different layers of abstraction contribute differently in the overall system reliability; if this contribution can be assessed independently, the reliability of the system can be evaluated at the early stages of the design. We review the state-of-the-art in the area and discuss corresponding challenges .