Richard Boyd Ericson

Non-causal behavior: The cause for concern

The requirement to verify the causality of electromagnetic model response and ensure validity of transient simulations results is gaining momentum for those skilled in the art. In order to capture causal models and verify causal behavior, the engineer must understand which parameters have an impact on model behavior as well as those parameters which inhibit lab verification of said model. Specifically, as dielectric properties continue to trend towards lower-loss, it may become more critical to understand the impact between dissipation factor and model causality. The SI engineer must have a keen understanding of the magnitude by which a models behavior can deviate from a causal response before he/she becomes concerned about their analysis. It is common knowledge that demand has and continues to drive computer systems data rates to ever-increasing speeds. As communication interface speeds increase, signal integrity engineers require more accuracy out of the transmission line models (models need to account for more effects). The level of accuracy now required has caused the complexity of transmission line models to increase to a point where concatenation of the models may induce significant error. As such, model developers must guarantee model behavior is causal, not merely frequency dependent. Non-causal models may generate inaccurate time domain simulation results as well as complicate a tools convergence process; even if the models behavior agrees with measured behavior in the frequency domain. Therefore, model developers must understand the model creation, checking, simulation process, and how to interpret results within chosen tool suites. Equally important, one must realize that model frequency content, step size, length and other parameters that may impact a checking tools ability to accurately flag causality violations and how those violations, “real” or “false”, may impact system-level simulation results [8]. This paper will discuss the interaction between the measured-model acquisition process, the ability to verify causal behavior and the ramifications of non-causal models or inaccurate interpretation of causality-checking results.

Extending lower-cost packaging technology into next generation signaling: Techniques and considerations

Current industry trends, combined with present cost pressures shall force signal integrity engineers to revisit traditional “rules of thumb” such that additional bandwidth can be obtained from conventional (standard) packaging materials and methodologies. In this paper, the authors assert that some current design practices prematurely cap the useful bandwidth of current technology, and unnecessarily lead designers to ask material scientists to solve our bandwidth concerns. Every facet of the electronics industry is subject to cost pressures. Opposite these financial constraints is the continuing drive to improve performance. Every new product must evaluate the business case for the use or inclusion of a new technology, more expensive component, or increase in power. The larger design community tends to move together into and out of technology “nodes” as they become more feasible and cost effective. Whether or not a particular technology is effective at meeting the design and business goals is a function of what other technologies and consequences are traded off in order to use it. This paper examines the conventional wisdom of some common practices, in light of an attempt to forego the use of advanced packaging technologies while extending the practical life of lower-cost techniques to signaling interfaces with higher frequency content.

Slot crossing and non-native IO voltage referencing: Effectiveness of image return capacitance to address signal integrity concerns

There is a growing requirement to thoroughly understand the tradeoffs made in “real-world” applications where package cross sections provide insufficient planes for both desirable IO referencing and DC current delivery. Allowing minimal split crossings and using significant decoupling are widely known design-guide “solutions”. It is also well known that slot crossing within any high-speed application should be avoided. This paper will perform a real-world study of current return paths on various carrier referencing structures and quantify, in terms of margin degradation, how concerning slot crossings really are and what can be done to mitigate these losses. This paper will not perform a “text-book” study of slot crossing phenomena; rather it will quantify Signal Integrity tradeoffs in modern, cross-section challenged, high-speed applications. This paper will discuss IO referencing, Signal Integrity, power distribution, decoupling, and cross-section trade-offs within an exemplary system including a high-speed memory application. Analysis will use a real-world example to quantify conventional implementation compromises and how each trade-off impacts performance, cost, design risk, and breaking points. Specifically, this paper will discuss and quantify: 1) The effect of interrupted reference planes on high-speed IO as frequency and the number of simultaneous switches varies 2) Margin degradation due to insufficient cross-sections creating mismatched driver IO and implemented reference voltages 3) Effectiveness of image return capacitors against IO referencing VCC that is not native to their driver supply