Richard Chapman

High level synthesis and generating FPGAs with the BEDROC system

Bedroc is a digital hardware synthesis system that automatically translates a behavioral description written in a hardware description language to field programmable gate arrays.Bedroc allows designers to specify their designs at a very high level of abstraction, and compile them into designs that can be realized in one of many different technologies. It can synthesize a wide variety of synchronous designs including signal processing applications, arithmetic applications, and general purpose processors. An additional aim of theBedroc project is to incorporate formal methods into the hardware synthesis process. By verifying the algorithms used for synthesis instead of the synthesized designs, we give the designer many of the benefits of formal methods without their having to learn new techniques. We have usedBedroc to synthesize several circuits from the High Level Synthesis Workshop benchmarks, including a wave digital elliptic filter.

Higher-order attribute grammars and editing environments

Attribute grammars [Knu68] serve as the underlying formal basis for a number of language-based environments and environment generators [DRTSl] [RT84] [SDB84] [JF85] [BC85] [Pfr86] [LMOWSS] [FZ89] [RT89] [BFHP89] [Jou89]. In such environments, attributes decorate an abstract-syntax-tree representation of an object being edited and are kept up to date as the underlying abstract-syntax tree is modified, either by direct user manipulation or by indirect transformation actions. The collection of attributes constitute a derived database of facts about the object. Attributes can provide immediate feedback that guides further user interaction, as in the case of error attributes indicating violations of context-sensitive conditions, and can also provide incremental translation, as in the case of objectcode attributes. A weakness of this firs&order attribute-grammar editing model is its strict separation of syntactic and semantic levels, with priority given to syntax. The attributes are completely constrained by their defining equations, whereas the abstract-syntax tree is unconstrained, except by the local restrictions of the underlying contextfree grammar. The attributes, which are relied on to communicate context-sensitive information throughout the syntax tree, have no way of generating derivation trees. They can be used to diagnose or reject incorrect syntax a posteriori but cannot be used to guide the syntax a priori. A few examples illustrate the desirability of permit-

Testing object-oriented programs: from formal specification to test scenario generation

Abstract New problems associated with the testing and maintenance of object-oriented programs (OOPs) have been introduced with the dramatically increasing use of OOPs over the past decade. Testing OOPs beyond the class level has been rarely discussed. This paper presents an approach performing high level testing for OOPs based on formal specifications and usage profiles. The behavior of a software system is specified in an object-oriented formal specification. A state model provides a complementary representation of the dynamic behavior. In the model, a state represents the cumulative results of the system behavior. Probability distributions are used to derive the anticipated operation sequences of a program from the state model. An enhanced state transition diagram (ESTD) is used to describe the state model, which incorporates hierarchy, usage and parameter information. This paper describes the construction of state transition diagrams (STDs) based on the formal specification, and the derivation of test scenarios from the ESTD.

Multiobjective particle swarm optimization

Evolutionary algorithms (EAs) are search procedures based on natural selection [2]. They have been successfully applied to a wide variety of optimization problems [4]. Particle Swarm Optimization (PSO) [1,7] is a new type of evolutionary paradigm that has been successfully used to solve a number of single objective optimization problems (SOPs). However, to date, no one has applied PSO in an effort to solve multiobjective optimization problems (MOPs). The purpose of our research is to demonstrate how PSO can be modified to solve MOPs. In addition to showing how this can be done, we demonstrate its effectiveness on two MOPs.

The BEDROC high level synthesis system

BEDROC is a digital hardware synthesis system that automatically translates a behavioral description written in a hardware description language to field programmable gate arrays. The authors have used BEDROC to synthesize several circuits from the high level synthesis workshop benchmarks. BEDROC is unusual in its aim to incorporate formal methods into the hardware synthesis process. By verifying the algorithms used for synthesis instead of the synthesized designs, the designer gets many of the benefits of formal methods without having to learn new techniques.<<ETX>>

VoiceLETS backs up first responders

VoiceLETS accesses data in the existing Law Enforcement Tactical System. LETS is a secure Web-based search engine designed to provide personal and vehicle information to law enforcement and criminal justice agencies. It integrates access to several state databases and currently includes photographs, addresses, personal characteristics, and driver and criminal histories from the states motor vehicles and corrections departments. The University of Alabamas CARE Research and Development Laboratory developed LETS with the goal of making it available to all qualifying agencies over the Internet, including patrol officers using mobile data terminals.

TEST SCENARIO GENERATION BASED ON FORMAL SPECIFICATION AND USAGE PROFILE

This paper presents a method for test scenario generation based on formal specifications and usage profiles. It is a major component of a framework for testing object-oriented programs. In this framework, the requirements of a software system are formally specified. The anticipated application of the system is expressed in a usage profile, which is a state model that indicates the dynamic behavior of the system and execution probabilities for the behaviors. The state model is used as a guide to derive the anticipated operation scenarios. An enhanced state transition diagram is used to represent the state model, which incorporates hierarchy, usage and parameter information. Since the number of feasible scenarios can be extremely large, probability and importance criteria are used to select the most probable and important scenarios.

Test scenario and regression test suite generation from Object-Z formal specification for object-oriented program testing

Regression testing is an important and costly activity in software maintenance. Not only the changed codes need to be tested, but it is also necessary to ensure that the changed code will not inadvertently a ect other functionalities. Because regression testing is expensive, automation has become an important issue. In this paper, we rst introduce a method for generating test scenarios, then we present a method for automatically generating usage-based regression test suites from an Object-Z formal speci cation. This method can be used in both integration and functional testing.

RTP and TCP based MIDI over IP protocols

In this paper we introduce a relatively large number of RTP and TCP based MIDI over IP protocols and perform statistically significant quantitative experiments on these protocols. We used two baseline simple and naïve TCP protocols, one with the Nagle algorithm disabled and one with the Nagle algorithm enabled. We want to determine which of the protocols would be best for performing a musical duet and which protocol would be satisfactory for the network transmission of a MIDI sequence. The MIDI (Musical Instrument Digital Interface) specification was created in 1983 and efforts to exploit this musical gesture language in networking protocols began in earnest in the 1990s. A unique design feature of the JMF (Java Media Framework) makes the utilization of reliable transport protocols such as TCP or SCTP possible for either the control channel or data channel or both channels of RTP.

Simulation of army unmanned aerial vehicle communications

We explore development of a high-fidelity simulation testbed for various network architectures for communication between components of tactical unmanned aerial systems, and for distribution of intelligence gathered by these systems.