Victor P. Nelson

Fault-tolerant computing: fundamental concepts

The basic concepts of fault-tolerant computing are reviewed, focusing on hardware. Failures, faults, and errors in digital systems are examined, and measures of dependability, which dictate and evaluate fault-tolerance strategies for different classes of applications, are defined. The elements of fault-tolerance strategies are identified, and various strategies are reviewed. They are: error detection, masking, and correction; error detection and correction codes; self-checking logic; module replication for error detection and masking; protocol and timing checks; fault containment; reconfiguration and repair; and system recovery.<<ETX>>

Extending integrated-circuit yield-models to estimate early-life reliability

The integrated yield-reliability model for integrated circuits allows one to estimate the yield, following both wafer probe and burn-in testing. The model is based on the long observed clustering of defects and the experimentally verified relation between defects causing wafer probe failures, and defects causing infant mortality failures. The 2-parameter negative binomial distribution is used to describe the distribution of defects over a semiconductor wafer. The clustering parameter /spl alpha/, while known to play a key role in accurately determining wafer probe yields, is shown, for the first time, to play a similar role in determining burn-in fall-out. Numerical results indicate that the number of infant mortality failures predicted by the clustering model can differ appreciably from calculations that ignore clustering. This is particularly apparent when wafer probe yields are low, and clustering is high.

Burn-in failures and local region yield: an integrated field-reliability model

Defects have long been known to cluster on semiconductor wafers. Recent research has shown that this fact may be exploited to produce die of high reliability, (i.e. decreased infant mortality), by sorting die into bins based on how many of their neighbors test faulty. Die that test good at wafer probe, yet come from neighborhoods with many faulty die, have a higher incidence of infant mortality failure than die from neighborhoods with few faulty die. Analysis of burn-in results from the SEMATECH test methods experiment suggests that such a binning approach has the potential to isolate a high quality bin that displays very few burn-in failures. This paper presents the first analytical model that quantifies the reliability improvement one might expect when binning die based on local region yield.

Estimating burn-in fall-out for redundant memory

Integrated circuits can exhibit significant early life or infant mortality failures. Methods to estimate and/or reduce the number of such failures are therefore of great interest to industry. Applications employing multi-chip modules (MCMs), where several die must be independently reliable, are particularly vulnerable to early life failures. Maximizing the reliability of each die is therefore of significant importance. This paper presents an integrated yield-reliability model that allows one to estimate the number of burn-in failures for repairable memory chips, a common component in many MCMs. Since defects in integrated circuits tend to cluster, memory chips that have been repaired have a greater chance of containing a latent defect than chips with no repairs. The result is a higher incidence of infant mortality failure among memory chips that have been repaired.

Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems

This paper presents a software based approach for automatic generation of digital circuitry for synthesis and incorporation in a mixed-signal circuit or system to provide Built-In Self-Test (BIST) and measurement of the analog circuitry. The measurements supported by the BIST circuitry include frequency response (both gain and phase), linearity and noise figure. The measurements provide analog functional testing as well as the basis for on-chip compensation to improve yield during manufacturing and performance during system operation.

Yield-reliability modeling for fault tolerant integrated circuits

An integrated yield-reliability model for defect tolerant integrated circuits is presented that allows one to estimate the yield following both wafer probe and burn-in testing. The model is based on the long observed clustering of defects and the experimentally verified relation between defects causing wafer probe failures and defects causing infant mortality failures. The two-parameter negative binomial distribution is used to describe the distribution of defects over a semiconductor wafer. The clustering parameter /spl alpha/, while known to play a key role in accurately determining wafer probe yields of defect tolerant chips, is shown for the first time. to play a similar role in determining burn-in fall-out. Numerical results indicate that the number of infant mortality failures predicted by the clustering model can differ significantly from calculations that ignore clustering.

A Microcomputer-Controlled Testing System for Digital Integrated Circuits

This paper describes a low-cost digital integrated circuit (IC) tester designed and implemented using the Intel 8080 microcomputer family. Test patterns are applied to each IC to be tested from a lookup table stored in memory, along with appropriate clock signals if needed. The resulting chip outputs are then examined for errors resulting from stuck-at conditions or other functional errors. The hardware and software structure are presented as well as experimental results obtained in actual system applications.

A Microcomputer-Based Controller for an Amusement Park Ride

The replacement of a hydraulic control system with a microcomputer adds flexibility, reliability, and safety to the operation of a parachute-drop ride.

Paper: Petri net performance modeling of a modified mesh-connected parallel computer

A new message-passing computer architecture called the modified mesh-connected parallel computer (MMCPC) is proposed and studied. The MMCPC is designed to be a general-purpose parallel architecture suitable for wafer scale integration. Stochastic Petri nets (SPN) are used to model the behavior of the MMCPC. Both the one-dimensional and two-dimensional SPN models of the MMCPC are presented.

CE2016: Updated computer engineering curriculum guidelines

Joint ACM/IEEE Computer Society undergraduate computer engineering curriculum guidelines are slated for release in 2016. These update the 2004 guidelines commonly known as CE2004. The presenters are part of the task group leading the revisions and will give an overview of the latest draft. Participants will engage in discussions on potential improvements to the guidelines to ensure that they are useful to programs as they work to ensure their curricula reflect the state-of-the-art in computer engineering education and practice and are relevant for the coming decade.