Richard Dorrance

Voltage-induced switching of nanoscale magnetic tunnel junctions

We demonstrate voltage-induced (non-STT) switching of nanoscale, high resistance voltage-controlled magnetic tunnel junctions (VMTJs) with pulses down to 10 ns. We show ~10x reduction in switching energies (compared to STT) with leakage currents <; 105 A/cm2. Switching dynamics, from quasi-static to the nanosecond regime, are studied in detail. Finally, a strategy for eliminating the need for external magnetic-fields, where switching is performed by set/reset voltages of different amplitudes but same polarity, is proposed and verified experimentally.

A scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-blas on FPGAs

Sparse Matrix-Vector Multiplication (SpMxV) is a widely used mathematical operation in many high-performance scientific and engineering applications. In recent years, tuned software libraries for multi-core microprocessors (CPUs) and graphics processing units (GPUs) have become the status quo for computing SpMxV. However, the computational throughput of these libraries for sparse matrices tends to be significantly lower than that of dense matrices, mostly due to the fact that the compression formats required to efficiently store sparse matrices mismatches traditional computing architectures. This paper describes an FPGA-based SpMxV kernel that is scalable to efficiently utilize the available memory bandwidth and computing resources. Benchmarking on a Virtex-5 SX95T FPGA demonstrates an average computational efficiency of 91.85%. The kernel achieves a peak computational efficiency of 99.8%, a >50x improvement over two Intel Core i7 processors (i7-2600 and i7-4770) and showing a >300x improvement over two NVIDA GPUs (GTX 660 and GTX Titan), when running the MKL and cuSPARSE sparse-BLAS libraries, respectively. In addition, the SpMxV FPGA kernel is able to achieve higher performance than its CPU and GPU counterparts, while using only 64 single-precision processing elements, with an overall 38-50x improvement in energy efficiency.

Design of a Fast and Low-Power Sense Amplifier and Writing Circuit for High-Speed MRAM

A high-speed and low-power prepared and write sense amplifier (PWSA) is presented for magnetoresistive RAM (MRAM). The sense amplifier incorporates a writing circuit for MRAM bits switched via timing of precessional dynamics (~GHz speed) in a magnetic tunnel junction (MTJ). By combining read and write functions in a single power-efficient circuit, the PWSA allows for fast read and write operations while minimizing the bit error rate after data programming. The PWSA circuit is designed based on a 65 nm CMOS technology, and the magnetic dynamics are captured by a Verilog-A compact model based on macrospin behavior for MTJs. Using the preread and comparison steps in the data program operation, we are able to reduce write power consumption by up to 50% under random data input conditions. Furthermore, using the voltage-controlled magnetic anisotropy effect for precessional switching, more than 10× reduction of write power and transistor size both in the memory cell and the write circuit is achieved, compared with using the spin transfer torque effect. The circuit achieves 2 ns read time, 1.8 ns write time, and 8 ns total data program operation time (consisting of two read steps, one write step, and a pass/fail check step) using this PWSA concept, and a 2× larger sensing margin through the current feedback circuit.

A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs)

With scaling of CMOS and Magnetic Tunnel Junction (MTJ) devices, conventional low-current reading techniques for STT-RAMs face challenges in achieving reliability and performance improvements that are expected from scaled devices. The challenges arise from the increasing variability of the CMOS sensing current and the reduction in MTJ switching current. This paper proposes a short-pulse reading circuit, based on a body-voltage sensing scheme to mitigate the scaling issues. Compared to existing sensing techniques, our technique shows substantially higher read margin (RM) despite a much shorter sensing time. A narrow current pulse applied to an MTJ significantly reduces the probability of read disturbance. The RM analysis is validated by Monte-Carlo simulations in a 65-nm CMOS technology with both CMOS and MTJ variations considered. Simulation results show that our technique is able to provide over 300 mV RM at a GHz frequency across process-voltage-temperature (PVT) variations, while the reference designs require 4.3 ns and 2.3 ns sensing time for a 200 mV RM, respectively. The effective read energy per bit required by the proposed sensing circuit is around 195 ft in the nominal case.

Diode-MTJ Crossbar Memory Cell Using Voltage-Induced Unipolar Switching for High-Density MRAM

This letter presents a diode-magnetic tunnel junction (MTJ) magnetic random access memory cell in a 65-nm complimentary metal-oxide-semiconductor compatible process. A voltage-controlled magnetic anisotropy switching mechanism, in addition to STT, allows for a unipolar set/reset write scheme, where voltage pulses of the same polarity, but different amplitudes, are used to switch the MTJs. A small crossbar array is constructed from 65-nm MTJs fabricated on a silicon wafer, with switching voltages ~ 1 V and thermal stability greater than 10 years, with discrete germanium diodes as access devices to allow for read/write operations. The crossbar architecture can be extended to multiple layers to create a 3-D stackable, nonvolatile memory with a sub-1F2 effective cell size.

Analysis of STT-RAM cell design with multiple MTJs per access

Density of STT-RAMs is limited by the area cost and width of the access device in a cell since it needs to support the programming currents. This paper explores a cell structure that shares each cells access transistor with multiple MTJ memory elements. Feasibility and limitations of such a cell structure is explored for both reading and writing of the memory. The analytical and simulation results indicate that only small amount of sharing is possible and having MTJs that can handle a high read current without disturbing the cell is needed.

A 190GFLOPS/W DSP for energy-efficient sparse-BLAS in embedded IoT

A DSP for sparse-BLAS is realized in 40nm CMOS. Featuring an efficient data stream reordering scheme and an intelligent, CSC-aware memory controller, the DSP achieves a peak energy efficiency of 190 GFLOPS/W at 0.6V, 160MHz, and a peak performance of 4.12 GFLOPS at 1V, 515MHz showing more than 6,600×, 2,700×, 1,100×, and 450× higher energy efficiency than state-of-the-art CPU, GPU, DSP, and FPGA hardware designs, respectively.