Richard Hammond

SiGe-free strained Si on insulator by wafer bonding and layer transfer

SiGe-free strained Si on insulator substrates were fabricated by wafer bonding and hydrogen-induced layer transfer of strained Si grown on bulk relaxed Si0.68Ge0.32 graded layers. Raman spectroscopy shows that the 49-nm thick strained Si on insulator structure maintains a 1.15% tensile strain even after SiGe layer removal. The strain in the structure is thermally stable during 1000 °C anneals for at least 3 min, while more extreme thermal treatments at 1100 °C cause slight film relaxation. The fabrication of epitaxially defined, thin strained Si layers directly on a buried insulator forms an ideal platform for future generations of Si-based microelectronics.

Extremely high transconductance Ge/Si/sub 0.4/Ge/sub 0.6/ p-MODFET's grown by UHV-CVD

Ge-channel modulation-doped field-effect transistors (MODFETs) with extremely high transconductance are reported. The devices were fabricated on a compressive-strained Ge/Si/sub 0.4/Ge/sub 0.6/ heterostructure with a Hall mobility of 1750 cm/sup 2//Vs (30,900 cm/sup 2//Vs) at room temperature (77 K). Self-aligned, T-gate p-MODFETs with L/sub g/=0.1 /spl mu/m displayed an average peak extrinsic transconductance (g(m/sub ext/)) of 439 mS/mm, at a drain-to-source bias voltage (V/sub ds/) of -0.6 V, with the best device having a value of g(m/sub ext/)=488 mS/mm. At 77 K, values as high as g(m/sub ext/)=687 mS/mm were obtained at a bias voltage of only V/sub ds/=-0.2 V. These devices also displayed a unity current gain cutoff frequency (f/sub T/) of 42 GHz and maximum frequency of oscillation (f/sub max/) of 86 GHz at V/sub ds/=-0.6 V and -1.0 V, respectively.

Scalability of strained-Si nMOSFETs down to 25 nm gate length

Strained-Si nMOSFETs with a standard polysilicon gate process were fabricated down to 25 nm gate length with well-behaved characteristics and small difference in short channel effects. The performance enhancement degrades linearly as the gate length becomes shorter, due to not only the parasitic resistance but also heavy halo implant. Thus the key integration issues are how to manage threshold difference and As diffusion without excess doping. With comparable doping and well controlled parasitic resistance, up to 45% improvement in drive current is predicted for sub-50 nm gate length strained-Si nMOSFETs on the Si/sub 0.8/Ge/sub 0.2/ substrate. In this work approximately 45% enhancement is in fact demonstrated for 35 nm gate length devices, through advanced channel engineering and implementation of metal gates.

p-Type SiGe transistors with low gate leakage using SiN gate dielectric

Using high-quality jet-vapor-deposited (JVD) SiN as gate dielectric, p-type SiGe transistors are fabricated on SiGe heterostructures grown by ultra-high-vacuum chemical vapor deposition (UHVCVD). For an 0.25-/spl mu/m gate-length device, the gate leakage current is as small as 2.4 nA/mm at V/sub ds/=-1.0 V and V/sub gn/=0.4 V. A maximum extrinsic transconductance of 167 mS/mm is measured. A unity current gain cutoff frequency of 27 GHz and a maximum oscillation frequency of 35 GHz are obtained.

SiGe pMODFETs on silicon-on-sapphire substrates with 116 GHz f/sub max/

The dc and microwave results of Si/sub 0.2/Ge/sub 0.8//Si/sub 0.7/Ge/sub 0.3/ pMODFETs grown on silicon-on-sapphire (SOS) substrates by ultrahigh vacuum chemical vapor deposition are reported. Devices with L/sub g/=0.1 /spl mu/m displayed high transconductance (377 mS/mm), low output conductance (25 mS/mm), and high gate-to-drain breakdown voltage (4 V). The dc current-voltage (I-V) characteristics were also nearly identical to those of control devices grown on bulk Si substrates. Microwave characterization of 0.1/spl times/50 /spl mu/m/sup 2/ devices yielded unity current gain (f/sub T/) and unilateral power gain (f/sub max/) cutoff frequencies as high as 50 GHz and 116 GHz, respectively. Noise parameter characterization of 0.1/spl times/90 /spl mu/m/sup 2/ devices revealed minimum noise figure (F/sub min/) of 0.6 dB at 3 GHz and 2.5 dB at 20 GHz.

Technique for producing highly planar Si/SiO0.64Ge0.36/Si metal–oxide–semiconductor field effect transistor channels

Si/Si0.64Ge0.36/Si heterostructures have been grown at low temperature (450 °C) to avoid the strain-induced roughening observed for growth temperatures of 550 °C and above. The electrical properties of these structures are poor, and thought to be associated with grown-in point defects as indicated in positron annihilation spectroscopy. However, after an in situ annealing procedure (800 °C for 30 min) the electrical properties dramatically improve, giving an optimum 4 K mobility of 2500 cm2 V – 1 s – 1 for a sheet density of 6.2 × 1011 cm – 2. The low temperature growth yields highly planar interfaces, which are maintained after anneal as evidenced from transmission electron microscopy. This and secondary ion mass spectroscopy measurements demonstrate that the metastably strained alloy layer can endure the in situ anneal procedure necessary for enhanced electrical properties. Further studies have shown that the layers can also withstand a 120 min thermal oxidation at 800 °C, commensurate with metal–oxide–semiconductor device fabrication.

High-performance SiGe pMODFETs grown by UHV-CVD

The fabrication and characterization of 0.1 /spl mu/m-gate-length SiGe pMODFETs fabricated on UHV-CVD-grown heterostructures with various novel layer structure configurations are reported. We have fabricated Ge-Si/sub 0.4/Ge/sub 0.6/ pMODFETs with peak extrinsic transconductance (g/sub max/) values as high as 488 mS/mm at room temperature. These devices also displayed a unity current gain cutoff frequency (f/sub T/) of 42 GHz and maximum frequency of oscillation (f/sub max/) of 86 GHz. We have also investigated the performance of Si/sub 0.2/Ge/sub 0.8/-Si/sub 0.7/Ge/sub 0.3/ pMODFETs on silicon-on-sapphire (SOS) substrates. These devices exhibited DC transconductances as high as g/sub max/=377 mS/mm, and had values of f/sub T/=49 GHz and f/sub max/=95 GHz. The first high-frequency noise characterization of SiGe MODFETs has also been performed. Si/sub 0.2/Ge/sub 0.8/-Si/sub 0.65/Ge/sub 0.35/ pMODFETs grown on high-p Si substrates produced minimum noise figures of 1.1 dB (2.9 dB) with an associated gain (G/sub a/) of 18 dB (7.6 dB) at 3 GHz (18 GHz).

Spin flip probability of electron in a uniform magnetic field

The probability that an electromagnetic wave can flip the spin of an electron is calculated. It is assumed that the electron resides in a uniform magnetic field and interacts with an incoming electromagnetic pulse. The scattering matrix is constructed and the time needed to flip the spin is calculated.

Low-noise SiGe pMODFETs on sapphire with 116 GHz f/sub max/

Recent advances in SiGe MODFET technology indicate that these devices may have promise for future high-speed analog communications applications (Adesida et al, 1997; Konig et al, 1998). However, losses and isolation problems due to the conducting Si substrate represent a serious disadvantage compared to III-V devices that utilize semi-insulating substrates. The use of insulating substrates such as sapphire is a potential solution to this problem, and previous results on Si and pseudomorphic SiGe-channel MOSFETs fabricated on silicon-on-sapphire (SOS) wafers have been encouraging (Johnson et al, 1998; Mathew et al, 1999). However, SiGe MODFETs require relaxed SiGe buffer layers, and the growth of high-quality relaxed SiGe on sapphire or SOS substrates has not previously been demonstrated. In this paper, we present the results of 0.1 /spl mu/m gate length pMODFETs fabricated on high-mobility Si/sub 0.2/Ge/sub 0.8/-Si/sub 0.7/Ge/sub 0.3/ quantum wells grown on SOS wafers. These devices displayed a power gain cut-off frequency (f/sub max/) of 116 GHz, and minimum noise figure (F/sub mm/) of 2.5 dB at 20 GHz. To our knowledge, these values are the best reported to date for pFETs in any material system.

RF systems based on silicon-on-sapphire technology

The major issues which confronted the formation of very thin layers of silicon (30-100 nm) on sapphire substrates for application to mm-wave communication and sensors were investigated. The focus of the investigation was to achieve a structure in which modern CMOS technology can be affordably continued. In this context the application of device-quality thin film silicon-on-sapphire (TFSOS), obtained by solid phase epitaxy (SPE), and the growth of strained silicon-germanium (SiGe) layers on these improved thin silicon films on sapphire have demonstrated enhanced device and circuit performance. We have fabricated 250 nm and 100 nm T-gated devices with noise figures as low as 0.9 dB at 2 GHz with an associated gain of 21 dB, and 2.5 dB at 20 GHz, with an associated gain of 7.5 dB, respectively. These performances resulted in distributed wide-band amplifiers (10 GHz BW) and tuned amplifiers (15 dB peak gain, 4 GHz BW), among others. Additionally, VCOs (25.9 GHz) and frequency dividers in excess of 30 GHz were fabricated with devices with f/sub t/(f/sub max/) of 105 GHz (50 GHz) for n-channel and 49 GHz (>110 GHz) for p-MODFETs with 100 nm T-gates (strained Si/sub 0.2/Ge/sub 0.8/ on a relaxed Si/sub 0.7/Ge/sub 0.3/ heterostructure).