S. J. Koester

SiGe-on-insulator prepared by wafer bonding and layer transfer for high-performance field-effect transistors

SiGe-on-insulator material was fabricated by wafer bonding and hydrogen-induced layer transfer techniques. The transferred SiGe layer is strain relaxed and has a Ge content ranging from 15% to 25%. High-quality strained Si layers were grown on the SiGe-on-insulator substrates by the UHV/chemical vapor deposition process at 550 °C. An electron mobility of 40 000 cm2/V s in a modulation-doped Si/SiGe heterostructure was achieved at 30 K on a SiGe-on-insulator substrate.

Extremely high transconductance Ge/Si/sub 0.4/Ge/sub 0.6/ p-MODFET's grown by UHV-CVD

Ge-channel modulation-doped field-effect transistors (MODFETs) with extremely high transconductance are reported. The devices were fabricated on a compressive-strained Ge/Si/sub 0.4/Ge/sub 0.6/ heterostructure with a Hall mobility of 1750 cm/sup 2//Vs (30,900 cm/sup 2//Vs) at room temperature (77 K). Self-aligned, T-gate p-MODFETs with L/sub g/=0.1 /spl mu/m displayed an average peak extrinsic transconductance (g(m/sub ext/)) of 439 mS/mm, at a drain-to-source bias voltage (V/sub ds/) of -0.6 V, with the best device having a value of g(m/sub ext/)=488 mS/mm. At 77 K, values as high as g(m/sub ext/)=687 mS/mm were obtained at a bias voltage of only V/sub ds/=-0.2 V. These devices also displayed a unity current gain cutoff frequency (f/sub T/) of 42 GHz and maximum frequency of oscillation (f/sub max/) of 86 GHz at V/sub ds/=-0.6 V and -1.0 V, respectively.

Evidence of electron and hole inversion in GaAs metal-oxide-semiconductor capacitors with HfO2 gate dielectrics and α-Si∕SiO2 interlayers

Evidence of inversion in GaAs metal-oxide-semiconductor capacitors with HfO2 gate dielectrics and α-Si∕SiO2 interlayers is reported. Capacitors formed on n-GaAs with atomic layer-deposited HfO2 displayed C-V characteristics with minimum Dit of 7×1011cm−2∕eV, while capacitors with molecular beam epitaxy-deposited HfO2 on p-GaAs had Dit=3×1012cm−2∕eV. Lateral charge transport was confirmed using illuminated C-V measurements on capacitors fabricated with thick Al electrodes. Under these conditions, capacitors on n-GaAs (p-GaAs) showed “low-frequency” C-V behavior, indicated by a sharp capacitance increase and saturation at negative (positive) gate bias, confirming the presence of mobile charge at the semiconductor/dielectric interface.

Effect of thermal processing on strain relaxation and interdiffusion in Si/SiGe heterostructures studied using Raman spectroscopy

The effect of thermal annealing on Si/SiGe heterostructures is studied using Raman spectroscopy. The structures consisted of Si on relaxed Si0.8Ge0.2 where the top Si thickness was 20–30 nm. Micro-Raman spectroscopy with 488 nm incident radiation revealed no significant shift in the strained Si peak position with thermal annealing at temperatures up to 1100 °C for 30 s. However, the intensity of the Si peak was systematically reduced with increasing thermal processing, a result which is attributed to interdiffusion at the Si/SiGe interface resulting in an apparent thinning of the Si cap layer.

SiGe pMODFETs on silicon-on-sapphire substrates with 116 GHz f/sub max/

The dc and microwave results of Si/sub 0.2/Ge/sub 0.8//Si/sub 0.7/Ge/sub 0.3/ pMODFETs grown on silicon-on-sapphire (SOS) substrates by ultrahigh vacuum chemical vapor deposition are reported. Devices with L/sub g/=0.1 /spl mu/m displayed high transconductance (377 mS/mm), low output conductance (25 mS/mm), and high gate-to-drain breakdown voltage (4 V). The dc current-voltage (I-V) characteristics were also nearly identical to those of control devices grown on bulk Si substrates. Microwave characterization of 0.1/spl times/50 /spl mu/m/sup 2/ devices yielded unity current gain (f/sub T/) and unilateral power gain (f/sub max/) cutoff frequencies as high as 50 GHz and 116 GHz, respectively. Noise parameter characterization of 0.1/spl times/90 /spl mu/m/sup 2/ devices revealed minimum noise figure (F/sub min/) of 0.6 dB at 3 GHz and 2.5 dB at 20 GHz.

Enhancement-Mode Buried-Channel

The operation of long- and short-channel enhancement-mode In0.7Ga0.3As-channel MOSFETs with high-k gate dielectrics are demonstrated for the first time. The devices utilize an undoped buried-channel design. For a gate length of 5 mum, the long-channel devices have Vt= +0.25 V, a subthreshold slope of 150 mV/dec, an equivalent oxide thickness of 4.4 +/ - 0.3 nm, and a peak effective mobility of 1100 cm2/Vldrs. For a gate length of 260 nm, the short-channel devices have Vt=+0.5 V and a subthreshold slope of 200 mV/dec. Compared with Schottky-gated high-electron-mobility transistor devices, both long- and short-channel MOSFETs have two to four orders of magnitude lower gate leakage.

\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As/In}_{0.52}\hbox{Al}_{0.48}\hbox{As}

We report on the dc and RF characterization of laterally scaled, Si-SiGe n-MODFETs. Devices with gate length, L/sub g/, of 80 nm had f/sub T/=79 GHz and f/sub max/=212 GHz, while devices with L/sub g/=70 nm had f/sub T/ as high as 92 GHz. The MODFETs displayed enhanced f/sub T/ at reduced drain-to-source voltage, V/sub ds/, compared to Si MOSFETs with similar f/sub T/ at high V/sub ds/.

MOSFETs With High-

Introduction. The ability to scale CMOS to future technology nodes is jeopardized primarily by power constraints. Supply voltage scaling is the best method to reduce power consumption in logic circuits; however, the thermionic nature of the turn-off mechanism in MOSFETs forces a fundamental trade-off between leakage power and performance when the voltage is reduced. Tunneling field effect transistors (TFETs) could overcome this limitation since these devices have been theoretically shown to be capable of subthreshold slopes < 60 mV/decade [1]. However, the band gap of silicon (1.12 eV) is too large to provide acceptable drive currents in Si-based TFETs. TFETs fabricated using Si/SiGe heterojunctions [2] have the potential for increased drive current since the type-II band alignment reduces the effective band gap for tunneling at the source electrode. In this talk, I will show experimental results on Si/SiGe heterojunction tunneling transistors (HETTs), along with quantum transport simulations on a variety of heterojunction TFET geometries, and then describe the implications of these results on the viability of the Si/SiGe material system for TFET fabrication. Si/SiGe HETTs. The devices were fabricated using a conventional CMOS process flow that was modified to allow the source and drain electrodes to be formed in separate processing steps. The devices utilized SOI starting substrates and a high-κ/poly gate stack. The n drain was formed by conventional As implantation and anneal, while the source electrode was formed by selective etching of Si underneath the gate electrode and regrowth of in-situ-doped p Si1-xGex. Typical Id vs. Vgs characteristics at room temperature for HETTs with source Ge concentrations of 7% and 25% are shown in Fig. 2 [3]. The improved performance for the devices with x = 25% over x = 7% provides a clear indication of the heterojunction benefit on TFET performance. However, the devices fall short of achieving sub-60 mV/dec subthreshold slopes or the necessary drive currents for practical applications. Broken-gap TFETs. In order to further explore the heterojunction band structure requirements for TFETs, quantum transport simulations are performance on a variety of HETTs with band alignment ranging from staggered to broken gap [4]. The results, shown in Fig.3, indicate that the optimal performance is achieved in broken-gap heterojunction devices. These results further demonstrate the efficacy of the heterojunction design in improving TFET drive current, but also suggest that novel device geometries [5] or material systems with direct band gaps (e.g. III-Vs [6], graphene nanoribbons [7]) may be needed to achieve the performance levels necessary for practical applications. References. [1] J. Appenzeller, et al., Phys. Rev. Lett., 2004, [2] O. Nayfeh, et al., IEEE Elect. Dev. Lett., 2008, [3] S. J. Koester, et al., unpublished, [4] S. Koswatta, et al., IEDM, 2009, [5] A. Bowander, et al., VLSI., 2008, [6] S. Mookerjea, et al., IEDM, 2009, [7] Q. Zhang, et al., IEEE Elect Dev. Lett., 2008. n+ poly

\kappa

The operation of long- and short-channel enhancement-mode In0.7Ga0.3As-channel MOSFETs with high-k gate dielectrics are demonstrated for the first time. The devices utilize an undoped buried-channel design. For a gate length of 5 mum, the long-channel devices have Vt= +0.25 V, a subthreshold slope of 150 mV/dec, an equivalent oxide thickness of 4.4 +/ - 0.3 nm, and a peak effective mobility of 1100 cm2/Vldrs. For a gate length of 260 nm, the short-channel devices have Vt=+0.5 V and a subthreshold slope of 200 mV/dec. Compared with Schottky-gated high-electron-mobility transistor devices, both long- and short-channel MOSFETs have two to four orders of magnitude lower gate leakage.

Gate Dielectrics

Abstract Nearly damage free etching of a high mobility Si SiGe heterostructure is obtained by using very low power reactive ion etching and precise end-point detection. Conductance versus wire width plots of 0.08 μm to 1 μm wide Si SiGe quantum well wires show the combined nonconducting width at the edges to be 0.13 μm ± 0.01 μm, in agreement with weak localization studies. Mobility vs. sheet concentration measurements indicate little or no degradation in electron mobility after processing. Furthermore, our study demonstrates very little difference between wires with and without post-RIE (reactive-ion etching) annealing and passivation treatment. Application of this process for fabricating point contacts and other quantum effect devices is demonstrated.