Richard Lossy

Reducing Thermal Resistance of AlGaN/GaN Electronic Devices Using Novel Nucleation Layers

Currently, up to 50% of the channel temperature in AlGaN/GaN electronic devices is due to the thermal-boundary resistance (TBR) associated with the nucleation layer (NL) needed between GaN and SiC substrates for high-quality heteroepitaxy. Using 3-D time-resolved Raman thermography, it is shown that modifying the NL used for GaN on SiC epitaxy from the metal-organic chemical vapor deposition (MOCVD)-grown standard AlN-NL to a hot-wall MOCVD-grown AlN-NL reduces NL TBR by 25%, resulting in ~10% reduction of the operating temperature of AlGaN/GaN HEMTs. Considering the exponential relationship between device lifetime and temperature, lower TBR NLs open new opportunities for improving the reliability of AlGaN/GaN devices.

Reliability issues of GaN based high voltage power devices

Abstract GaN based power devices for high efficiency switching applications in modern power electronics are rapidly moving into the focus of world wide research and development activities. Due to their unique material properties GaN power devices are distinguished by featuring high breakdown voltages, low on-state resistances and fast switching properties at the same time. Finally, these properties are the consequences of extremely high field and current densities that are possible per unit device volume or area. Therefore, in order to obtain very high performance, the material itself is stressed significantly during standard device operation and any imperfection may lead to wear out and reliability problems. Thus material quality, the specific epitaxial design as well as the device topology will directly influence device performance, reliability and mode of degradation. The paper will mainly discuss those degradation mechanisms that are especially due to the specific material combinations used in GaN based high voltage device technology such as epitaxial layer design, chip metallization, passivation schemes and general device topology and layout. It will then discuss technological ways towards engineering reliability into these devices. Generally, device designs are required that effectively minimize high field regions in the internal device or shift them towards less critical locations. Furthermore, an optimized thermal design in combination with suitable chip mounting technologies is required to enable maximum device performance.

Influence of GaN cap on robustness of AlGaN/GaN HEMTs

DC-Step-Stress-Tests of GaN HEMTs have been performed on wafers with and without GaN-cap. The tests consist of a step ramping of drain-source voltage VDS by 5V every two hours at off-state. The irreversible evolution of leakage current starting at a certain drain voltage has been taken as a criterion for the onset of device degradation. It has been stated that there is a stability limit for VDS depending on the epitaxial design. It has been found that wafers with GaN cap show much higher critical voltages as compared to non-capped epitaxial designs. Electroluminescence measurements have been performed to localize defects after DC-Step-Stress-Tests up to 80V for wafer without GaN cap and 120V for wafer with GaN cap.

AlGaN/GaN HEMT With Integrated Recessed Schottky-Drain Protection Diode

We present an AlGaN/GaN high-electron mobility transistor (HEMT) with an integrated recessed protection diode on the drain side of the transistor channel. Results from our Schottky-drain HEMT demonstrate an excellent reverse blocking with minor tradeoff in the on-state resistance for the complete device. The excellent quality of the forward diode characteristics indicates high robustness of the recess process. The reverse blocking capability of the diode is better than - 110 V. Physical-based device simulations give an insight in the respective electronic mechanisms. This is the first time that a recessed Schottky-drain diode integrated in a HEMT device is presented.

Laser-assisted processing of VIAs for AlGaN/GaN HEMTs on SiC substrates

Vertical interconnect accesses (VIAs) were fabricated between the source electrode on the front and the ground on the backside of high-power microwave AlGaN/GaN high-electron mobility transistors (HEMTs) on /spl sim/400-/spl mu/m-thick silicon carbide substrates. Through-wafer microholes with an aspect ratio of up to /spl sim/ 8 were drilled using pulsed UV-laser machining and subsequently metallized using electroplating. The successful implementation of the laser-assisted VIA technology into device processing was proven by dc and RF characterization. When biased at 26 V, a saturated output power of 41.6 W with an associated power-added efficiency of 55% at 2 GHz was achieved for a 20-mm AlGaN/GaN HEMT with through-wafer VIAs.

Gallium nitride MIS-HEMT using atomic layer deposited Al2O3 as gate dielectric

Metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) were fabricated with an AlGaN/GaN heterostructure. The ALD-deposited Al2O3 layer served as gate dielectric under the gate electrode and as passivation layer in the access region. Different processing routes were tested and confirm that choosing the optimum order of processing steps is required to take full advantage of MIS-HEMT capabilities. Gate leakage currents as low as 2 × 10−10 A/mm at VGS = −20 V were measured. They are 4 orders of magnitude lower compared to the Schottky reference. Also, drain leakage went down to 10−8 A/mm and thus reduced by 3½ decades compared to the Schottky-type. The corresponding on/off-ratio rates 108. The subthreshold swing improved considerably from 180 mV/dec for the Schottky type to 90 mV/dec for the MIS-HEMT. Breakdown voltage is >200 V for a gate-drain distance >4 μm. From S-parameter measurements ft = 18 GHz and fmax = 72 GHz were extrapolated.

Large Area AlGaN/GaN HEMTs Grown on Insulating Silicon Carbide Substrates

Large periphery Al 0.25 Ga 0.75 N/GaN-HEMTs on SiC-substrates are fabricated on a 2-inch process line using stepper lithography. DC characteristics reveal current densities above 1.2 A/mm and intrinsic transconductances of 360 mS/mm. Depending on device size the maximum frequency of oscillation f max varies from 27-79 GHz. With these devices a power density of 5.2 W/mm and a power level of 13.8 W is achieved at 2 GHz.

Characterization of stress degradation effects and thermal properties of AlGaN/GaN HEMTs with photon emission spectral signatures

The influence of stress degradation and device temperature variation on the device properties has been investigated with electrical and photon emission (PE) measurements. To degrade the devices the type of short-time stress tests, namely DC-Step-Stress-Tests of GaN HEMTs have been performed on wafers with and without GaN cap to additionally check the behaviour of various technological processes. It has been found that wafers with GaN cap show much higher critical voltages as compared to non-capped epitaxial designs and have different PE spectral signatures. Thermo-electrical topics like high power dissipation and self-heating of GaN based HEMTs were also investigated with electrical characterization and electroluminescence in various operating conditions.

Single image spectral electroluminescence (photon emission) of GaN HEMTs

Continuous spectra of GaN HEMT photon emission were detected with prism-based optical path. Full spectra are obtained with single emission images by expansion of the emission spot to a spectral tail. Therefore, multi-finger HEMTs require FIB inactivation of excess fingers to ensure single finger operation. The extracted parameter is electron temperature correlated to kinetic energy of the 2DEG electrons. It is field-related and scales with gate voltage, in agreement with device simulation. No spectral peaks were detected.

Influence of the device geometry on the Schottky gate characteristics of AlGaN/GaN HEMTs

In this work, we investigate the relevance of device geometry to the Schottky gate characteristics of AlGaN/GaN high electron mobility transistors. Changes of three-terminal gate turn-on voltage and gate leakage current on the gate—drain spacing, source—gate spacing and recess depth have been observed. Further examinations comparing device simulations and measurements suggest that gate turn-on voltage is influenced by the distribution of electric potential under the gate region which is related to the geometry. By proper design of the device, high gate turn-on voltage can be obtained for both depletion-mode and recessed enhancement-mode devices.