Richard Nicholas Iachetta

Method and apparatus for allowing multi-speed synchronous communications between a processor and both slow and fast computing devices

Apparatus and method for protecting system serial number while allowing motherboard replacement

Method and apparatus for implementing power-saving sleep mode in design with multiple clock domains

Non-uniform memory access (NUMA) data processing system that buffers potential third node transactions to decrease communication latency

Method and system for avoiding data loss due to cancelled transactions within a non-uniform memory access system

Target directed completion for bus transactions

Non-uniform memory access (NUMA) data processing system that decreases latency by expediting rerun requests

Method and apparatus for preserving the contents of synchronous DRAM through system reset

System and method for providing improved bus utilization via target directed completion

Queue having distributed multiplexing logic