Richard Perdriau

A Direct Power Injection Model for Immunity Prediction in Integrated Circuits

This paper introduces a complete simulation model of a direct power injection (DPI) setup, used to measure the immunity of integrated circuits to conducted continuous-wave interference. This model encompasses the whole measurement setup itself as well as the integrated circuit under test and its environment (printed circuit board, power supply). Furthermore, power losses are theoretically computed, and the most significant ones are included in the model. Therefore, the injected power level causing a malfunction of an integrated circuit, according to a given criterion, can be identified and predicted at any frequency up to 1 GHz. In addition to that, the relationship between immunity and impedance is illustrated. Simulation results obtained from the model are compared with measurement results, and these demonstrate the validity of this approach.

EMC Assessment at Chip and PCB Level: Use of the ICEM Model for Jitter Analysis in an Integrated PLL

This paper deals with the use of the integrated circuit electromagnetic model (ICEM) to analyze, predict, and optimize autocompatibility and electromagnetic emission at chip and system level. ICEM is currently under standardization process (IEC62014-3). The basic ICEM architecture is composed of a power distribution network model and an internal current source modeling digital activity. Such an approach enables the description of any kind of digital or mixed-signal design. This model is useful either for the IC manufacturer or the system manufacturer. The power distribution network of a printed circuit board (PCB) can be optimized using this model by choosing the number and the right values of decoupling capacitors as well as the size of power planes. The IC manufacturer may check out the autocompatibility of an IC and determine the number of power pins as well as the package to be used. As an example, jitter analysis of an integrated phase-locked-loop can be performed using ICEM. This paper demonstrates that this jitter can be predicted by simulation and that corrective solutions can be provided and checked out before implementation

ICEM modelling of microcontroller current activity

Abstract Better prediction of electromagnetic compatibility (EMC) for components is becoming a topical demand due to technology improvements. It is requested by integrated circuit (IC) manufacturers as well as by equipment integrators. The French UTE standardisation group has proposed an EMC modelling methodology for ICs, called integrated circuit electromagnetic model (ICEM). This proposal improves and extends the IBIS standard towards conducted emission prediction (and later radiated emission) by providing additional information modelling the power network and the dynamic current activity of an IC, thus allowing the chip manufacturer to justify the package used as well as the number of power supply pins, and the equipment manufacturer to tune power supply and decoupling networks. After a brief introduction to the ICEM model and the associated methods, this article shows a way of obtaining dynamic current activity models by measuring the current consumed on the IC power supply pins. The use of ICEM for the optimisation of decoupling networks, the evaluation of power supply noise and the tuning of the surface of power and ground planes is presented for the first time with subsequent results.

Investigation on ESD Transient Immunity of Integrated Circuits

This paper presents a measurement methodology aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. In our application, a very fast transmission line pulsing (VF-TLP) test bench is used to inject a disturbance into an IC under operation. For simulation purposes, each part of the test bench is modeled separately, and these models are assembled in order to obtain a complete model representing both the injection set-up and the IC itself. The suggested injection model is validated thanks to correlations between measurements and simulations on a full- custom 0.18 mum CMOS IC.

Efficiency of Embedded On-Chip EMI Protections to Continuous Harmonic and Fast Transient Pulses with Respect to Substrate Injection

This paper presents a comparative study of the efficiency of several embedded EMI protections for integrated circuits (ICs) with respect to direct power injection (DPI) and very fast transmission-line pulsing (VF-TLP) into the substrate of the IC. This study involves three functionally identical cores, differing only by their EMI protection strategies (RC protection, isolated substrate, meshed power supply network) which were initially designed for low-emission design guidelines. Through extensive measurements, a classification between these strategies is established for both injection methods, leading to the introduction of design guidelines for the minimization of conducted susceptibility to substrate injection.

Comparison among emission and susceptibility reduction techniques for electromagnetic interference in digital integrated circuits

This paper presents a comparative study of susceptibility reduction techniques for electromagnetic interference (EMI) in digital integrated circuits (ICs). Both direct power injection (DPI) and very-fast transmission-line pulsing (VF-TLP) methods are used to inject interference into the substrate of a single test chip. This IC is built around six functionally identical cores, differing only by their EMI protection strategies (RC protection, isolated substrate, meshed power supply network) which were initially designed for low emission design rules. The ranking of three of these cores in terms of electromagnetic immunity is then compared with the one of their radiated emission, thanks to near-field scanning (NFS) measurements. This leads to the establishing of design guidelines for low EMI in digital ICs.

Assessment of the Immunity of Unshielded Multi-Core Integrated Circuits to Near-Field Injection

This paper presents a comparative assessment of the electromagnetic immunity of 4 integrated logic cores to near-field injection. These cores, located on the same die, are identical from a functional point of view, but differ by their design strategies. The injection is performed above each core according to the 6 components of the electromagnetic field, using appropriate probes. These results demonstrate that the die and bondwires of an integrated circuit can be sensitive to both magnetic and electric fields, and that some design rules can improve the immunity of integrated circuits to near-field interference.

Simple, Taylor-Based Worst-Case Model for Field-to-Line Coupling

To obtain Electromagnetic Compatibility (EMC), we would like to study the worst-case electromagnetic field-induced voltages at the ends of Printed Circuit Board (PCB) traces. With increasing frequencies, modelling these traces as electrically short no longer suffices. Accurate long line models exist, but are too complicated to easily induce the worst case. Therefore, we need a simple analytical model. In this article, we predict the terminal voltages of an electrically long, two-wire transmission line with characteristic loads in vacuum, excited by a linearly polarised plane wave. The model consists of a short line model (one Taylor cell) with an intuitive correction factor for long line effects: the modified Taylor cell. We then adapt the model to the case of a PCB trace above a ground plane, illuminated by a grazing, vertically polarised wave. For this case, we prove that end-fire illumination constitutes the worst case. We derive the worst-case envelope and try to falsify it by measurement in a Gigahertz Transverse Electromagnetic (GTEM) cell.

Electrical modeling of inductive links for high-efficiency energy transmission

This paper presents an innovative modeling method for the mutual inductance of two magnetically coupled coils in an inductive link, ensuring efficient energy and data transmission in implantable electronic devices. An electrical model, which can be used within a circuit simulator, directly takes into account the lateral and longitudinal displacements between the external coil (transmitter) and the internal coil (receiver), thus enabling to optimize the voltage gain of the link, and opening to the design of inductive links with high power transfer capabilities and high overall efficiency.

Detection of Electromagnetic Interference in Microcontrollers Using the Instability of an Embedded Phase-Lock Loop

This paper presents a combined hardware-software mechanism for the detection of electromagnetic interference of a microcontroller (μC) in daily usage. This detection mechanism is based on the instability of phase-lock loop embedded in the target μC. It can detect the presence of EMI with higher sensitivity than polling the hardware status of the μC internal registers and thus provides a better detection margin within the 10 kHz to 1 GHz EMI frequency range. Despite its relative slowness and its resource consumption, it is very robust, can be implemented in virtually any application software, and does not require any electromagnetic compatibility test equipment.