Etienne Sicard

The Electromagnetic Compatibility of Integrated Circuits—Past, Present, and Future

Throughout the decades of continuous advances in semiconductor technology, from the discrete devices of the late 1950s to todays billon-transistor system-on-chip, there have always been concerns about the ability of components to operate safely in an increasingly disruptive electromagnetic environment. This paper provides a nonexhaustive review of the research work conducted in the field of electromagnetic compatibility (EMC) at the IC level over the past 40 years. It also brings together a collection of information and trends in IC technology, in order to build a tentative roadmap for the EMC of ICs until the year 2020, with a focus on measurement methods and modeling approaches.

The challenge of signal integrity in deep-submicrometer CMOS technology

Advances in interconnect technologies, such as the increase in the number of metal layers, stacked vias, and the reduced routing pitch, have played a key role to continuously improve integrated circuit design and operating speed. However several parasitic effects jeopardize the benefits of scale-down. Understanding and predicting interconnect behavior is vital for designing high-performance integrated circuit design. Our paper first reviews the interconnect parasitic effects and examines their impact on circuit behavior and their increase due to lithography reduction, with special emphasis on propagation delay, lateral coupling, and crosstalk-induced delay. The problem of signal integrity characterization is then discussed. In our review of the different well-established measurement methodologies such as direct probing, S-parameters, e-beam sampling and on-chip sampling, we point out weaknesses, frequency ranges, drawbacks, and overall performances of these techniques. Subsequently, the on-chip sampling system is described. This features a precise line-domain characterization of the voltage waveform directly within the interconnect and shows its application in the accurate evaluation of propagation delay, crosstalk, and crosstalk-induced delay along interconnects in deep-submicrometer technology. The sensor parts are described in detail, together with signal integrity patterns and their implementation in 0.18-/spl mu/m CMOS technology. Measurements obtained with this technique are presented. In the third part, we discuss the simulation issues, describe the two- and three-dimensional interconnect modeling problems, and review the active device models applicable to deep-submicrometer technologies in order to agree on measurements and simulations. These studies result in a set of guidelines concerning the choice of interconnect models. The last part outlines the design rules to be used by designers and their implementation within computer-aided design (CAD) tools to achieve signal integrity compliance. From a 0.18-/spl mu/m technology are derived critical variables such as crosstalk tolerance margin, maximum coupling length, and the criteria for adding a signal repeater. From these, values for low-dielectric and copper interconnects have been selected.

Electromagnetic Compatibility of Integrated Circuits

The electromagnetic compatibility (EMC) community, usually concerned with noise and interference at the electronic-system level, has recently focused more attention on integrated circuits (ICs). This review concentrates upon the recent advances in microelectronics technology, the understanding of internal couplings within ICs, parasitic emission, and susceptibility to radiofrequency interference. Highlights of measurement techniques, modeling, and design approaches are also proposed in this paper.

Modeling the Electromagnetic Emission of a Microcontroller Using a Single Model

This paper presents a methodology for building an integrated circuit behavioral model that enables the prediction of its electromagnetic (EM) emissions up to several gigahertz. The model, built upon S-parameter characterization and conducted emission measurements, is used to predict the EM emissions of a commercial 16-bit microcontroller. The emission measurements are performed according to several EM compatibility standards, namely, 1 Omega /150 Omega , surface scan, and transverse EM/gigahertz transverse EM (GTEM) method, and their results show an excellent fit with model predictions.

Characterization and modeling of parasitic emission in deep submicron CMOS

This paper presents a study of the parasitic emissions of a 0.18-/spl mu/m CMOS experimental integrated circuit (IC) and an accurate method for modeling the internal current switching to forecast electromagnetic interference (EMI). The effectiveness of emission reduction techniques is quantified through a set of conducted noise measurements. A simple core model is developed, based on the current switching activity. Added to a lumped-element model of the test board and the package, good agreement between simulation and measurements are obtained up to 10 GHz. The simulation methodology may be applied to forecast the impact of low emission design techniques on the EMI of ICs.

Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits

This paper introduces a low cost near-field mapping system. This system scans automatically and dynamically, in the time domain, the magnetic field emitted by integrated circuits during the execution of a repetitive set of instructions. Application of this measurement system is given to an industrial chip designed with a 180nm CMOS process. This application demonstrates the efficiency of the system but also the helpfulness of the results obtained to identify paths followed by the current, enabling to locate the potential IR drop zones.

Towards an EMC roadmap for Integrated Circuits

The following document gathers a collection of information and trends about integrated circuit (IC) technology to build a tentative roadmap for ElectroMagnetic Compatibility (EMC) of ICs until year 2020, with focus on embedded system-on-chip (SoC) for automotive and consumer electronics applications.

On-chip sampling in CMOS integrated circuits

This paper presents a technique for precise crosstalk delay measurement based on on-chip sampling. Results obtained on a test chip fabricated in 0.7-/spl mu/m CMOS technology exhibit a 100% delay increase in a long coupled line configuration.

Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools

This paper presents the strategies used for effective teaching and skill development in integrated circuit (IC) design using project-based learning (PBL) methodologies. It presents the contexts in which these strategies are applied to IC design courses at the University of South Australia, Adelaide, Australia, and the National Institute of Applied Science (INSA), Toulouse, France. Collaborations among the faculty members of the two institutions have produced a set of learning resources and design tools to support the development of industry-relevant design skills and lifelong learning skills. At the pedagogical level, the emphasis is on the development of practical circuit design, critical thinking, and problem-solving skills rather than the mastery of complex circuit design tools. The courses enable students to learn about the most recent technological developments and their implications, using a set of user-friendly tools. The PBL methodologies, intuitive design tools, and latest technology models have consistently produced high levels of student satisfaction with the overall quality of the courses at the two institutions.

Analysis of crosstalk interference in CMOS integrated circuits

The authors show how crosstalk coupling between transmission lines inside CMOS integrated circuits can provoke faulty behavior by affecting the propagation delay of the logic and analog cells. A simplified model for the evaluation of parasitic capacitive coupling effects is proposed, and the influence of crosstalk on the behavior of basic functions such as logic gates, latches, RAM memory, and analog-to-digital converters is evaluated. >