Richard R. Oehler

IBM RISC System/6000 processor architecture

This paper describes the hardware architecture of the IBM RISC System/6000 processor, which combines basic RISC principles with a partitioning of registers by function into multiple ALUs. This allows a high degree of parallelism in execution and permits a compiler to generate highly optimized code to manage the interaction among parallel functions. Floating-point arithmetic is integrated into the architecture, and floating-point performance is comparable to that of many vector processors.

An IBM second generation RISC processor architecture

A second-generation RISC (reduced-instruction-set computer) architecture designed to support superscalar implementations which can execute multiple instructions every cycle is described. The architecture provides compound function instructions which allow application path lengths to be less than would be required on many complex-instruction-set computers. This second-generation RISC architecture also exploits advances in optimizing compiler and operating system technology. An extension to the original 801 minicomputer virtual memory architecture for hardware support of database storage is described.<<ETX>>

IBM RISC System/6000: architecture and performance

The IBM RISC System/6000, a superscalar microprocessor, is presented. The architecture of this processor has its instruction set specifically designed for a superscalar machine containing three independent units-branch, fixed-point, and floating-point. The design also emphasizes high-performance floating-point operations. The design principles are to offer maximum overlap of the three functional units, avoid dead cycles, and define instructions that can (for the most part) be completed at a rate of one per cycle. The branch cycle, fixed- and floating-point units, cache management, and performance are described. Benchmark results are given.<<ETX>>

RISC System/6000 processor architecture

Abstract The 801 minicomputer 1 project at IBM Research in Yorktown Heights, NY, USA, in 1975 pioneered many of architectural concepts used in RISC including IBMs RT System. The paper describes a second-generation RISC architecture, the POWER architecture, which is based on subsequent research by the original 801 team and is used in the recently announced RISC System/6000. The architecture was designed to support superscalar implementations which can execute multiple instructions every cycle. It provides compound-function instructions which allow application path lengths to be less than would be required on many complex instruction set computers. The architecture also exploits advances in optimizing compiler and operating system technology. An extension to the original 801 virtual memory architecture for hardware support of database storage is also described.