Richard Reiner

Assembly and Packaging Technologies for High-Temperature and High-Power GaN Devices

This paper gives a detailed analysis on the assembly and packaging technologies for the state-of-the-art GaN-based high-electron-mobility transistors, which are suitable for high-temperature and high-power applications. Silver sintering and transient liquid phase bonding were selected as die-attachment techniques, and gold and palladium were investigated for electrical interconnection materials. Both the die-attachments were characterized for their high-temperature stability up to 450 °C. Systematic electrical characterizations were performed from on-wafer measurements to the final assembly. The thermal and thermomechanical influences of the assembly were assessed. For die-attachments and interconnections, passive temperature shock cycling and active power cycling were performed as an initial attempt to characterize the assembly reliability. Finally, a complete package along with the base plate was proposed, which can survive high temperatures up to 480 °C.

Benchmarking of Large-Area GaN-on-Si HFET Power Devices for Highly-Efficient, Fast-Switching Converter Applications

This work reports the development and fabrication of large area AlGaN/GaN-on-Si HFETs for the use in highly-efficient fast-switching power converters. High performance is demonstrated by full characterization of static- and dynamic-parameters and a direct comparison to two commercial state-of-the-art silicon power devices. Compared to their silicon counterparts the GaN-device achieves by a factor of 3 lower static area specific on-state resistance RON×A, and by a factor of 3 lower static on-state resistance times gate charge product RON×Q. In switching tests the device achieves a low dynamic dispersion and low switching losses. Furthermore in this work a sophisticated measurement setup for characterization of dynamic parameters is developed and demonstrated. Characterization and test conditions are adapted for the use in fast-switching power converter applications.

Integrated reverse-diodes for GaN-HEMT structures

This work introduces an enhanced GaN-HEMT structure that uses separated Schottky contacts as integrated free-wheeling diodes for the reverse operation. The principle is investigated and compared to other integrated reverse-diode concepts. Different diode structures are fabricated and evaluated. The new concept is demonstrated on a large gate width 600 V-device with on-state currents up to 30 A and an on-state resistance of 215 mΩ. Furthermore, the device achieves a very low gate-charge of below 3 nC and a reverse recovery charge of 8 nC.

Quasi-normally-off GaN gate driver for high slew-rate d-mode GaN-on-Si HEMTs

This work presents a quasi-normally-off gallium nitride (GaN) transistor with positive gate threshold voltage based on depletion-mode technology, suitable for gate drivers or logic circuits. Quasi-normally-off behaviour is achieved by the series connection of multiple Schottky diodes in the source path of an initially normally-on transistor. As opposed to conventional approaches, a novel quasi-normally-off gate driver circuit avoids the static shoot-through current path in the driver final stage and ensures a safe blocking state of a d-mode power switch in case of driver failure with only one negative driver supply voltage. For evaluation a hybrid integrated GaN power module is built, comprising a 2.4 A gate driver and 600 V/ 24 A boost converter switching cell. Measurements of pulsed inductive switching up to 274 V/ 12 A show gate voltage rise and fall times of 5.4 ns and 3.8 ns, boost converter switch node transition times as low as 1.6 ns and 1.2 ns, and maximum slew-rates up to 91 V/ns during turn-on transitions, and up to 177 V/ns during turn-off transitions, respectively.

Assembly and packaging technologies for high-temperature and high-power GaN HEMTs

In this work, assembly and packaging technologies for high-temperature high-power GaN high electron mobility transistors (HEMTs) are presented. GaN HEMTs with epitaxial growth on Silicon substrates were used during these experiments. Both die-attachment and interconnection techniques were investigated and a performance comparison is given before and after the assembly process. State-of-the-art silver sintering and transient liquid phase bonding were used as die-attachment methods [2], [3]. For the die-attach material, various characterizations such as shear strength, Energy Dispersive X-ray (EDX) spectroscopy and Differential Scanning Calorimetery (DSC) were performed to characterize the operation up to 500 °C. An estimation of the thermal behavior of the sintered and TLP-bonded GaN HEMTs is performed. For interconnection, gold- and palladium-based materials were investigated for wire-bonding. The complete bonding process was characterized. Estimations about the current carrying capabilities are made for both materials. Passive temperature cycling from -40 to +150 °C was performed as an indication of initial reliability for both die-attachments and interconnections. A systematic electrical characterization of HEMTs is performed starting from the on-wafer measurements up to the final assembly process. The influence of thermal effects on the electrical properties, such as on-state reIn this work, assembly and packaging technologies for high-temperature high-power GaN high electron mobility transistors (HEMTs) are presented. GaN HEMTs with epitaxial growth on Silicon substrates were used during these experiments. Both die-attachment and interconnection techniques were investigated and a performance comparison is given before and after the assembly process. State-of-the-art silver sintering and transient liquid phase bonding were used as die-attachment methods. For the die-attach material, various characterizations such as shear strength, Energy Dispersive X-ray (EDX) spectroscopy and Differential Scanning Calorimetry (DSC) were performed to characterize the operation up to 500 °C. An estimation of the thermal behavior of the sintered and TLP-bonded GaN HEMTs is performed. For interconnection, gold- and palladium-based materials were investigated for wire-bonding. The complete bonding process was characterized. Estimations about the current carrying capabilities are made for both materials. Passive temperature cycling from -40 to +150 °C was performed as an indication of initial reliability for both die-attachments and interconnections. A systematic electrical characterization of HEMTs is performed starting from the on-wafer measurements up to the final assembly process. The influence of thermal effects on the electrical properties, such as on-state resistance at higher power levels, i.e., 350 W were studied before and after the assembly process. A combination of sintered device with the gold wire bonds is considered as the optimum packaging of GaN HEMTs.sistance at higher power levels, i.e., 350 W were studied before and after the assembly process. A combination of sintered device with the gold wire bonds is considered as the optimum packaging of GaN HEMTs.

Trapping Effects at the Drain Edge in 600 V GaN-on-Si HEMTs

In this paper, we investigate the influence of the drain electrode on the dynamic switching behavior of AlGaN/GaN high-electron-mobility transistors on Si substrate. By adding a field plate to the drain electrode, a dramatic increase in the dynamic ON-resistance dynRON was identified. The dispersion effect is correlated with the high electric field below the drain field plate (DFP), the onset of which is caused by the full electron depletion from both the channel and the GaN cap layer. We show that the electron distribution is modified by the passivation method, backside bias, or surface charges and, hence, shifts the onset voltage of the trapping effect. Trapped electrons underneath the DFP are thought to be responsible for the measured rise of the dynRON. With the introduction of an extended ohmic drain contact, the influence of a metallization overhang at the drain edge can be suppressed. The detrapping energies associated with the surface defects were determined to 0.2, 0.3, and 0.7 eV, respectively. Simulations and measurements indicate that charges inside the passivation below the DFP worsen the switching behavior.

GaN HEMTs and MMICs for space applications

We report on recent results from our GaN transistor and circuit technology. Epitaxial growth can be performed on either SiC or Si substrates in order to provide high-quality AlGaN/GaN heterostructures. These heterostructures are then utilized in order to realize transistors and integrated circuits ranging from high-voltage transistors for voltage conversion in efficient power switches, L/S-band power bars and X-band MMICs for next-generation communication systems, and finally W-band MMICs for radar applications. The technology is characterized by state-of-the-art performance, good uniformity and high yield as well as excellent long-term stability. In combination with the space compatibility we believe that this technology is ideal for space. X-band MMICs from Fraunhofer IAF are scheduled to have the first in-orbit demonstration of European GaN within the Proba-V mission which is planned to be launched in spring 2013.

Fractal structures for low-resistance large area AlGaN/GaN power transistors

This work introduces a new design approach for the use of fractal structures for low-resistance large area transistors structures. Aspects of layout with adapted current density and high-area utilization are considered. Furthermore the work presents a realization of fractal structures in AlGaN/GaN technology. Both static and dynamic behaviors are characterized. The fabricated devices achieve a breakdown voltage of VBR >; 700V and on-state currents of ID = 40A at VGS = 1V.

Thermal Stability and Failure Mechanism of Schottky Gate AlGaN/GaN HEMTs

This paper investigates the electrothermal stability and the predominant defect mechanism of a Schottky gate AlGaN/GaN HEMT. Calibrated 3-D electrothermal simulations are performed using a simple semiempirical dc model, which is verified against high-temperature measurements up to 440 °C. To determine the thermal limits of the safe operating area, measurements up to destruction are conducted at different operating points. The predominant failure mechanism is identified to be hot-spot formation and subsequent thermal runaway, induced by large drain-gate leakage currents that occur at high temperatures. The simulation results and the high temperature measurements confirm the observed failure patterns.

High-voltage stress time-dependent dispersion effects in AlGaN/GaN HEMTs

In this work we investigate the dispersion effects of GaN based HEMTs as a function of the off-state stress voltage and the stress time. We characterize the reduction of the drain current in on-state after off-state stress time from 2 μs up to 10 s. In addition, we compare different source- and gate-terminated field plate configurations. High-voltage (HV) pulsed stress tests with several stress rates are carried out to measure the increase of dynamic on-resistance over time. A new analytic model is developed to estimate the relevant trapping and detrapping time constants of the devices. By HV pulsed stress tests at different temperatures it is possible to estimate the activation energies for both processes.