Richard Schinella

Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure

Method and apparatus for application of proximity correction with unitary segmentation

Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench

Method for creating self-aligned alloy capping layers for copper interconnect structures

Optical corrective techniques with reticle formation and reticle stitching to provide design flexibility

Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning

Process for planarizing upper surface of damascene wiring structure for integrated circuit structures

Low k dielectric composite layer for intergrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning

Method of making self-aligned remote polysilicon contacts

Method of forming SiGe gate electrode