Wilbur G. Catabay

Copper drift in methyl-doped silicon oxide film

Drift of copper (Cu) ions into methyl-doped silicon oxide film, a promising low-dielectric-constant (low-κ) material for inter-layer dielectrics applications in ultralarge scale integrated circuit (ULSI) interconnects, was investigated using bias temperature stressing (BTS)/capacitance–voltage (C–V), current–voltage (I–V) at elevated temperatures and time-dependent dielectrics breakdown (TDDB) tests. Standard and control metal–insulator–semiconductor capacitor test samples with “sandwich” dielectric layer structures were used in the tests. BTS in nitrogen (N2) ambient at an electric field magnitude up to 1.5 MV/cm and with temperatures between 175 and 275 °C was used to accelerate the Cu ion drift. By studying flat band voltage shift in C–V tests, leakage current magnitude in I–V tests and time to fail in TDDB tests, it is demonstrated that Cu ions readily drift into methyl-doped silicon oxide under electric fields at elevated temperatures. Results obtained using different techniques correlate well to eac...

Chemical Mechanical Polishing of Low Dielectric Constant Oxide Films Deposited Using Flowfill Chemical Vapor Deposition Technology

In this work, the properties and chemical mechanical polishing (CMP) characteristics of thin films of a new low dielectric constant (low-κ) oxide deposited using Flowfill chemical vapor deposition (CVD) technology are presented. This oxide film consists of silicon dioxide network with methyl groups incorporated and has a dielectric constant K as low as ∼2.7. The film properties were studied using Fourier transform infrared spectroscopy (FTIR), spectroscopic ellipsometry, Rutherford backscattering, atomic force microscopy, and capacitance-voltage measurements. The refractive index, as low as 1.38, was measured using spectroscopic ellipsometry. The surface was found to be more hydrophobic compared to conventional CVD oxide. The stretching mode of the Si-O bond peak in the FTIR spectrum shifts to lower wavenumber, which corresponds to lower Si-O bonding energy, with increase in the methyl concentration inside the film. The CMP removal rate decreases as the methyl concentration in the film increases. An atomically smooth surface with root mean square surface roughness <1 nm over an area 2 X 2 μm was obtained after CMP. Our results suggest that the incorporation of methyl groups results in a reduction in the CMP removal rate. We speculate that the diffusion of water into the film is probably the CMP removal rate-limiting step.

An overview of stress free polishing of Cu with ultra low-k(k<2.0) films

An overview of the process performance of Stress Free Polishing technology (SFP) for copper removal at sub 90 nm nodes is presented in this paper. A brief description of the SFP process and polishing characteristics is provided along with electrical results. Dependence of post SFP copper surface quality on the roughness of the incoming films and post plating anneal conditions is also discussed.

Deposition and Characterization of Polycrystalline Si1 − x Ge x Films for CMOS Transistors Gate Electrode Applications

Polycrystalline Si 1 - x Ge x (poly-SiGe) is a known gate electrode material that can mitigate poly-depletion effects, which exist in deep submicrometer complementary metal-oxide-semiconductor (CMOS) transistors, due to its lower dopant activation temperatures and smaller bandgaps. As an important step toward the manufacturing of poly-SiGe electrode-based CMOS transistors with enhanced performances, this study focuses on the deposition of poly-SiGe films with different structural features and the characterization of the physical properties of these films. The electrical performance and the reduction in poly-depletion effects of the poly-SiGe electrodes in capacitors fabricated using these films were verified using capacitance-voltage measurements.

Process Characterization and Control of Polycrystalline SiGe as the Gate Electrode in CMOS Fabrication

Polycrystalline Si 1 - x Ge x (poly-SiGe) films have been proposed as a promising alternative to the currently employed polycrystalline silicon (poly-Si) gate electrode for complementary metal-oxide-semiconductor (CMOS) field effect transistor technology due to lower resistivity, less boron penetration, and less gate depletion than that of poly-Si gate. The use of Poly-SiGe as the gate electrode, however, has serious implications on transistor fabrication processes such as plasma dry etching, resist ashing, wafer cleaning, and oxidation. In this work, we investigate the impact of these processes on the polycrystalline Si 1 - x Ge x profile and the critical dimension (CD) of the gate electrode. The process improvements and an integration scheme using an oxide liner are presented to minimize the profile and CD variations introduced by the fabrication processes.

Process integration of Cu metallization and ultra low k (k=2.2)

The first process integration of Cu metallization and next generation CVD ultra low k (Trikon Orion ULK, k=2.2) is presented. The current process condition for a 130 nm node Cu/lowk (k=2.9) process is applied to Cu/ULK and found to be suitable without major modifications. The comparison of post CMP measurement (dishing, erosion, peeling, and scratch) show no significant variation between control (k=2.9) and ULK. The electrical data indicates the successful integration of Cu and ULK. The interconnect capacitance is expected to reduce 20% at 0.1 /spl mu/m technology node using the ULK film.

Implementation of a carbon doped low-k material for 0.18 micron technology

In the development of interconnect architecture for future technologies, LSI has determined that adoption of low-k dielectrics will give higher performance gain as opposed to the replacement of aluminum with copper. The goal is to integrate a robust low-k material for LSIs 0.18 /spl mu/m subtractive aluminum technology with at least 20% capacitance reduction. As a result we have successfully integrated and qualified a flowable carbon doped low-k-film. Dielectric constant ranges from 2.8 to 3.5. We have achieved comparable via resistance performance and 20% to 35% reductions in the line-to-line capacitance compared to the conventional HDP scheme. Greater than 90% system uptime was obtained during the marathon. The process has been released to manufacturing with statistical process control monitoring for the past few months.