Rick E. Presley

Thin-film transistors with amorphous indium gallium oxide channel layers

Indium gallium oxide-based thin-film transistors (TFTs) are formed using rf magnetron sputtering of the channel layer. These TFTs exhibit qualitatively ideal characteristics, including excellent drain current saturation. Various deposition parameters, annealing treatments, and stoichiometries are explored. Varying the oxygen partial pressure is found to have a significant effect on device performance. Decreasing the oxygen partial pressure increases the incremental channel mobility μinc while decreasing (becomes more negative) the turn-on voltage Von. Increasing indium concentration of the channel material increases μinc, while decreasing Von. The maximum value of μinc, ∼27cm2V−1s−1, is obtained by annealing at 600°C, with corresponding Von and drain current on-to-off ratio values of approximately −14V and >106, respectively. Additionally, TFTs subjected to a 200°C postdeposition annealing exhibit μinc and Von of ∼19cm2V−1s−1 and 2V, respectively.

Mapping out the distribution of electronic states in the mobility gap of amorphous zinc tin oxide

Amorphous zinc tin oxide (ZTO) is a wide-band-gap (transparent) semiconductor which exhibits high electron mobilities irrespective of its disordered nature. Transient photocapacitance (TPC), drive level capacitance profiling (DLCP), and modulated photocurrent spectroscopy (MPC) were used to determine the electronic state distribution within the mobility gap of ZTO. Conduction band-tail and valence band-tail Urbach energies near 10 and 110 meV were obtained by MPC and TPC, respectively. DLCP indicated free carrier densities in the mid-1015 cm−3 range plus a 0.2eV wide band of defects 0.4eV from the conduction band. The MPC spectra for ZTO also disclosed a defect band near the conduction band-tail.

Bias stress stability of zinc-tin-oxide thin-film transistors with Al2O3 gate dielectrics

The bias stability of zinc-tin-oxide (ZTO) thin-film transistors (TFTs) with either Al2O3 gate dielectrics deposited via atomic layer deposition (ALD) or SiO2 gate dielectrics deposited via plasma-enhanced chemical vapor deposition (PECVD) was compared. Both device types showed incremental mobility ≥11 cm2/V s, subthreshold slopes <0.4 V/dec, and ION/IOFF ratios of ∼107. During repeated ID-VGS sweeping, both device types showed positive parallel shift of the turn-on voltage (VON) without significant degradation of subthreshold slope or mobility, consistent with electron trapping without creation of new traps. A smaller VON shift was observed in the SiO2/ZTO devices. In an effort to improve the bias stress stability of the Al2O3/ZTO devices, the impact of ALD temperature, plasma exposure of the Al2O3, and the addition of an interfacial PECVD SiO2 capping layer were investigated. The positive bias stress stability of the Al2O3/ZTO TFTs was found to be relatively unaffected by the Al2O3 ALD temperature, degr...

Passivation of Amorphous Oxide Semiconductors Utilizing a Zinc–Tin–Silicon–Oxide Barrier Layer

Sputter-deposited amorphous zinc-tin-silicon-oxide (ZTSO) is demonstrated to be a viable electronic passivation layer for bottom-gate thin-film transistors (TFTs) with amorphous zinc-tin-oxide and indium-gallium-zinc-oxide channels. ZTSO allows for successful passivation of these semiconductors without significant changes in turn-on voltage, hysteresis, or channel mobility that is commonly associated with unsuccessful passivation of amorphous oxide semiconductors (AOSs). Passivation of AOS TFTs using ZTSO significantly increases electrical stability under negative-bias illumination stress testing conditions compared with unpassivated AOS TFTs. ZTSO also acts as a barrier layer allowing for additional postprocessing (e.g., plasma-enhanced chemical vapor deposition processes) that in some cases can negatively effect an unprotected AOS layer.

AC/DC Rectification With Indium Gallium Oxide Thin-Film Transistors

Two circuits to accomplish ac/dc rectification using thin-film transistors (TFTs) based on amorphous oxide semiconductors are presented. The TFTs are implemented using either indium gallium oxide or zinc tin oxide as the channel layer material. One circuit is a full-bridge configuration while the second uses a cross-tied configuration to increase the output voltage. With an input of 7.07 V rms at a frequency of 1 MHz, output voltages of ~ 9 and ~ 10.5 V, respectively, are observed. With a channel length of 15 ¿m, successful operation up to 20 MHz is demonstrated.

Bias Stability of zinc-tin-oxide thin film transistors with Al 2 O 3 gate dielectrics

Zinc-tin-oxide (ZTO) thin film transistors (TFTs) with atomic layer deposition (ALD) Al<inf>2</inf>O<inf>3</inf> gate dielectrics were fabricated and compared to devices with PECVD SiO<inf>2</inf> gate dielectrics. The Al<inf>2</inf>O<inf>3</inf> devices showed acceptable mobility (∼14 cm²/V·s), subthreshold slope (∼0.4 V/dec), and I<inf>ON</inf>/I<inf>OFF</inf> (∼10⁷). However, a pronounced positive V<inf>T</inf> shift was observed during initial gate voltage sweeps, consistent with electron trapping. In an effort to stabilize operation, devices were made with varying Al<inf>2</inf>O<inf>3</inf> deposition temperature, O<inf>2</inf> plasma exposure, and a plasma-enhanced chemical vapor deposited (PECVD) SiO<inf>2</inf> capping layer. It was found that capping of the Al<inf>2</inf>O<inf>3</inf> with a thin (2–3 nm) layer of PECVD SiO<inf>2</inf> altered the trapping behavior and reduced the bias instability significantly, suggesting that the Al<inf>2</inf>O<inf>3</inf>/ZTO interface is the source of the trapping.