Riichiro Shirota

New Method to Analyze the Shift of Floating Gate Charge and Generated Tunnel Oxide Trapped Charge Profile in NAND Flash Memory by Program/Erase Endurance

A new test system was devised and used to separate the amount of floating gate (FG) charge (QFG) from the oxide trapped charge (QOX) generated by program-and-erase (P/E) cycles. We also extracted the pure Vmid shift caused by the generation of QOX, which is separated from the part of Vt shift coming from QFG deviation. The identification of QFG and Vmid shift makes it possible to analyze the detailed the oxide trapped charge profile. The QFG shift generated by P/E cycles displays asymmetry between the programmed and erased states: the absolute value of QFG exhibits a maximum at ~100 cycles in the programmed states, while QFG monotonically decreases in the erased one. Considering that the Fowler-Nordheim tunneling current is sensitive to the oxide trap near the cathode, itself the source of electron tunneling current, our results indicate that the hole trap is dominant near to Si, whereas the electron trap is dominant near FG.

Analysis of the Correlation Between the Programmed Threshold-Voltage Distribution Spread of nand Flash Memory Devices and Floating-Gate Impurity Concentration

The effect of the activated floating-gate (FG) impurity concentration on the programmed threshold-voltage ( Vt) distribution was newly investigated and analyzed. The lower FG impurity concentration leads to a wider threshold-voltage distribution, which is explained by the time-dependent tunnel-oxide electric-field enhancement effect induced by the reduction of the depletion region in the FG as the programming time is lengthened. Initially, the FG is deeply depleted at the interface of the tunnel oxide. However, as the programming time is prolonged, electrons by Fowler-Nordheim (FN) tunneling in the FG generate electron-hole pairs, and generated holes are gathered at the interface of the tunnel oxide, which reduces the depletion region, and enhance the oxide electric filed. The enhancement effect of the electric field for the tunnel oxide is coupled to the FN tunneling statistics and enlarges the distribution of the programmed Vt. This effect is more clearly observed at the lower FG impurity concentration, which gives the limitation of the minimum impurity concentration in FG. Monte Carlo simulations considering both the tunnel-oxide electric-field enhancement effect and FN tunneling statistics were carried out and showed good agreement with the experiments.

Impact of Source/Drain Junction and Cell Shape on Random Telegraph Noise in NAND Flash Memory

A comprehensive numerical study of threshold voltage fluctuation (ΔVT) in scaled NAND flash memory caused by random telegraph noise (RTN) and discrete dopant fluctuation (RDF) in both the channel and the cell-to-cell space [source/drain (S/D)] region was carried out. Following a three-dimensional (3D) Monte Carlo (MC) procedure, the statistical distribution of ΔVT is estimated, considering the effects of both the random placement of discrete doping atoms and a discrete single trap at the tunnel oxide/substrate interface. The result demonstrates the significant influence of the doping in the S/D regions. For the cells with and without an S/D junction, the electron concentration in the S/D region is determined by the pass voltage of the unselected cell (Vpass) and the neighboring cell VT (VT(n)), owing to the fringing fields of neighboring floating gates (FGs). As a result, ΔVT increases in the S/D region as Vpass - VT(n) decreases. The fluctuation amplitude strongly depends on the [single-trap RTN] position along the cell length (L) and width (W) directions. For the cell shape with rounding of the active area (AA) at the shallow trench isolation (STI) edge, the results indicate that the high ΔVT area moves from the AA edge towards the center area along the W-direction.

A New Programming Scheme for the Improvement of Program Disturb Characteristics in Scaled nand Flash Memory

This paper investigates the new programming scheme to reduce the program disturb in the NAND Flash memory. Program disturb characteristics are determined by the unwilling electron injections in the floating gate of the unselected cells during programming. Thus, the key point to improve the program disturb characteristics is how to suppress the electron injection in the unselected cells. This requirement can be implemented by reducing the number of electrons in the unselected NAND strings prior to programming. By applying negative bias to all the word lines in the selected block, excess electrons can be removed from the channel and source/drain regions into the bit line or the source line using drift and diffusion mechanisms, and also electrons in the surface states can be recombined with accumulated holes before programming. After the pretreatment of electron reduction in the NAND string, a normal NAND program sequence follows. The advantage of the pretreatment before programming has been verified by measuring the 8-Gb NAND Flash memory with a 50-nm technology node. Significant reduction of the threshold voltage shift was observed even after the severe program disturb stress, which corresponds to around 30 times of the programming of the 2 bit/cell operation.

A new disturb free programming scheme in scaled NAND Flash memory

New programming scheme is proposed to improve the program disturb characteristics in NAND Flash memory named Program Disturb Free Scheme (PDFS), which is executed by removing excess electrons from the channel and source/drain into bit line or source line using drift-diffusion mechanism, and also by recombining electrons in the surface states with accumulated holes before programming. Thus, no excess electron exists in the program inhibit cell string during programming, thereby program disturb can be suppressed drastically. By measuring 8Gbit NAND Flash memory with 50nm technology node, almost no Vt shift was observed even applying 30 times over programming (partial programming) in 2bit/cell operation. This universally applicable innovation is independent from generation of design rule. Therefore, new operation has broken new ground for the cell device engineering, especially for sub-30nm NAND which has seriously narrowed program operation margin.

Analytical Model to Evaluate the Role of Deep Trap State in the Reliability of NAND Flash Memory and Its Process Dependence

An elementary step of trap and detrap processes of electron in the tunnel oxide during program/erase in NAND Flash memory is precisely studied. Owing to the high electric field during program and erase (P/E), the electron trapping and detrapping occur at the same time. Consequently, the detrapping process only leaves electrons in the deeper trap energy state (Etrap) than 3.5 eV. In addition, as-grown trap density (Ne) and capture cross section (σ) in the deep trap state can be specified to explain the measured data including the tunneling current modulation with cycling and the VT shift by oxide trap. The P/E endurance characteristics using dry and plasma oxidation processes are analyzed and compared. In both processes, σ has the same value (~4 × 10-17 cm2). However, Ne depends on the oxidation process. In dry oxidation, Ne is ~1.88 × 1019 cm-3. On the other hand, in plasma oxidation, 30% reduction (~1.25 × 1019 cm-3) can be found.

Improvement of oxide reliability in NAND flash memories using tight endurance cycling with shorter idling period

It has been newly found that shorter intervals between program and erase operations can suppress the oxide degradation more significantly in a 0.05 to 5 sec timeframe. Our new analysis clearly demonstrates the following degradation phenomena: a longer interval yields more trapped charges near the Si surface and surface states. Our results also indicate that the oxide degradation occurs more significantly during the erase-to-program interval than in the program-to-erase interval. These findings suggest that the erasing step causes a self-induced positive FG potential yields an accumulation of trapped holes near the Si surface and also generates surface states during the interval from erase-to-program. In addition, regarding retention characteristics, larger Vt shifts caused by the reduction of surface states and electron detrapping of oxide charges are observed in the longer interval. Based on these results, a new NAND operation scheme is proposed to improve reliability in shorter intervals.

Characterization of the charge trapping properties in p-channel silicon–oxide–nitride–oxide–silicon memory devices including SiO2/Si3N4 interfacial transition layer

The role of SiO2/Si3N4 interfacial transition (IFT) layer in the oxide–nitride–oxide (ONO) tri-layer is quantitatively analyzed for the first time by simulating the temperature and stress-accelerated retention characteristics of p-channel silicon–oxide–nitride–oxide–silicon (SONOS) devices. The ONO tri-layer is modeled as an alloy-dielectric by changing the atomic concentration of silicon, oxygen and nitrogen. It is revealed that simulated results including the IFT layer are more consistent with the experimental data than those neglecting the IFT layer. In addition, the results show that the trapped charge density in IFT layer is two times larger than in the bulk Si3N4 film, due to the oxygen atoms penetrated from SiO2 cause the extrinsic defects in the IFT layer. The energy levels of the trapped charge are continuously distributed, and the peak value is ~1.6 eV below the conduction band of the ONO tri-layer with a full width at half maximum of 0.45 eV.

Study Trapped Charge Distribution in P-Channel Silicon-Oxide-Nitride-Oxide-Silicon Memory Device Using Dynamic Programming Scheme

In this study, we precisely investigate the charge distribution in SiN layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon–oxide–nitride–oxide–silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in SiN layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking.