Yung-Yueh Chiu

A unified 3D device simulation of random dopant, interface trap and work function fluctuations on high-к/metal gate device

In this work, we for the first time estimate total fluctuation resulting from random dopants (RDs), interface trap (ITs) and work functions (WKs) using experimentally calibrated 3D device simulation on 16-nm-gate high-к/metal gate devices. The total 3D simulated threshold voltage fluctuation (σVth), induced by the aforementioned random sources simultaneously, is 55.5 mV for NMOS; however, a statistical total sum of these fluctuations is 12.3% overestimation because independence assumption on random variables is invalid owing to strong interactions among RDs, ITs and WKs. Devices DC/AC and CMOS SRAM circuit fluctuations have similar observation. FinFET-based structure innovation possessing large fluctuation suppression (σVth = 30.2 mV; 45.6% reduction), compared with process efforts on planar one, is further discussed.

New Method to Analyze the Shift of Floating Gate Charge and Generated Tunnel Oxide Trapped Charge Profile in NAND Flash Memory by Program/Erase Endurance

A new test system was devised and used to separate the amount of floating gate (FG) charge (QFG) from the oxide trapped charge (QOX) generated by program-and-erase (P/E) cycles. We also extracted the pure Vmid shift caused by the generation of QOX, which is separated from the part of Vt shift coming from QFG deviation. The identification of QFG and Vmid shift makes it possible to analyze the detailed the oxide trapped charge profile. The QFG shift generated by P/E cycles displays asymmetry between the programmed and erased states: the absolute value of QFG exhibits a maximum at ~100 cycles in the programmed states, while QFG monotonically decreases in the erased one. Considering that the Fowler-Nordheim tunneling current is sensitive to the oxide trap near the cathode, itself the source of electron tunneling current, our results indicate that the hole trap is dominant near to Si, whereas the electron trap is dominant near FG.

Dual-Material Gate Approach to Suppression of Random-Dopant-Induced Characteristic Fluctuation in 16 nm Metal--Oxide--Semiconductor Field-Effect-Transistor Devices

In this work, we explore for the first time dual-material gate (DMG) and inverse DMG devices for suppressing the random-dopant (RD)-induced characteristic fluctuation in 16 nm metal–oxide–semiconductor field-effect-transistor (MOSFET) devices. The physical mechanism of suppressing the characteristic fluctuation of DMG devices is observed and discussed. The achieved improvement in suppressing the RD-induced threshold voltage, on-state current, and off-state current fluctuations are 28, 12.3, and 59%, respectively. To further suppress the fluctuations, an approach that combines the DMG method and channel-doping-profile engineering is also advanced and explored. The results of our study show that among the suppression techniques, the use of the DMG device with an inverse lateral asymmetric channel-doping-profile has good immunity to fluctuation.

3D simulation of electrical characteristic fluctuation induced by interface traps at Si/high-к oxide interface and random dopants in 16-nm-Gate CMOS devices

The random dopant (RD)-induced threshold voltage fluctuation (σVth) was explored recently [1–4]. RD fluctuation (RDF) has been one of challenges in nano-CMOS technologies; consequently, high-к/metal gate (HKMG) approach is adopted to suppress intrinsic parameter fluctuation and leakage current for sub-45-nm generations. However, random interface traps (ITs) appearing at Si/high-к oxide interface results in a new fluctuation source [2]. Effects of ITs and RDs on electrical characteristic fluctuation have not been explored yet. In this work, we study influences of random ITs and RDs on 16-nm CMOS devices using an experimentally calibrated 3D device simulation [1–4]. Devices with totally random ITs, RDs, and “ITs+RDs” (i.e., 3D device simulation with considering random ITs and RDs simultaneously) are generated and simulated to assess the device variability.

Correlation between interface traps and random dopants in emerging MOSFETs

In this work, we for the first time study the fluctuation and interaction between interface traps (ITs) and random dopants (RDs) of 16 nm MOSFETs. Totally random devices with 2D ITs at Si/high-к oxide interface and 3D RDs inside channel are simultaneously examined using an experimentally validated 3D device simulation. Pure random ITs at Si/high-к oxide interface will increase the threshold voltage (Vth) due to enlarge potential barrier resulting from accept-like ITs. However, the fluctuation of Vth (σVth) induced by ITs is smaller than the result of RDs. Considering the effect of ITs and RDs at the same time will result in coupled localized spikes of potential barrier and induced characteristics are much more correlated to each other which can not be estimated using adiabatic statistical sum calculation. Consequently, the effect of random ITs and RDs on device variability should be counted simultaneously for high-к / metal gate devices.

Characterization of the charge trapping properties in p-channel silicon–oxide–nitride–oxide–silicon memory devices including SiO2/Si3N4 interfacial transition layer

The role of SiO2/Si3N4 interfacial transition (IFT) layer in the oxide–nitride–oxide (ONO) tri-layer is quantitatively analyzed for the first time by simulating the temperature and stress-accelerated retention characteristics of p-channel silicon–oxide–nitride–oxide–silicon (SONOS) devices. The ONO tri-layer is modeled as an alloy-dielectric by changing the atomic concentration of silicon, oxygen and nitrogen. It is revealed that simulated results including the IFT layer are more consistent with the experimental data than those neglecting the IFT layer. In addition, the results show that the trapped charge density in IFT layer is two times larger than in the bulk Si3N4 film, due to the oxygen atoms penetrated from SiO2 cause the extrinsic defects in the IFT layer. The energy levels of the trapped charge are continuously distributed, and the peak value is ~1.6 eV below the conduction band of the ONO tri-layer with a full width at half maximum of 0.45 eV.

High mobility InGaZnO thin film transistor using narrow-bandgap titanium-oxide semiconductor as channel capping layer

Metal-oxide InGaZnO thin-film transistors (IGZO TFTs) have received substantial attention as potential substitutes for amorphous Si and/or polycrystalline Si in active-matrix liquid-crystal displays, active-matrix organic light emitted diodes (AMOLEDs), and three-dimensional (3D) display applications [1]-[2]. It is well known that the multi-alloy IGZO channel plays an important role in device characteristics such as subthreshold swing (SS) and field-effect mobility (μFE). Although the high-K gate dielectrics to lower operating voltage and threshold voltage (VT) of TFT devices have demonstrated [3]-[5], these critical issues on transfer characteristics still need to be overcome. The large SS and low μFE prevent them from being applied in fast-switching and high-resolution displays. In this paper, we demonstrate high mobility IGZO TFT with titanium oxide (TiOx) channel capping layer. Large μfe of 66 cm2/Vs and low SS of 79 mV/dec were achieved using narrow-bandgap TiOx (Eg~ 3.1eV) [6] with optimized 5-nm thickness. The similar bandgap and conduction band offset to those of IGZO are favorable to obtain a low resistance ohmic contact between amorphous IGZO and Al contact metals.

Study Trapped Charge Distribution in P-Channel Silicon-Oxide-Nitride-Oxide-Silicon Memory Device Using Dynamic Programming Scheme

In this study, we precisely investigate the charge distribution in SiN layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon–oxide–nitride–oxide–silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in SiN layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking.