Rinat Shimshi

Dynamic defect-limited yield prediction by criticality factor

In this paper, we present a new methodology for inline yield prediction based on defect inspection and design data. We derive a new metric called criticality factor (CF), which is essentially a fractional critical area for a defect of the reported size in a small layout window around the reported defect location. CF would be a good predictor of yield if geometrical considerations alone determined whether an electrical fail will result. Since other properties of the defect affect the electrical outcome (such as material properties), we employ a Training Set of wafers where the functional relation between CF and die yield is learned for each critical inspection step. From that point on these curves are used to predict the yield impact of in-line defects for new wafers. In addition, we show that highly-systematic defects (i.e. layout dependent) deviate from the CF functional curves, and hence add noise to the calculation. We suggest a technique to separate these defects from the random population, and calculate a corrected CF value for them.

Integrated electrical and SEM-based defect characterization for rapid yield ramp

Challenges of the new nanometer processes have complicated the yield enhancement process. The systematic yield loss component is increasing, due to the complexity and density of the new processes and the designs that are developed for them. High product yields can now only be achieved when process failure rates are on the order of a few parts per billion structures. Traditional yield ramping techniques cannot ramp yields to these levels and new methods are required. This paper presents a new systematic approach to yield loss pareto generation. The approach uses a sophisticated Design-of-Experiments (DOE) approach to characterize systematic and random yield loss mechanisms in the Back End Of the Line (BEOL). Sophisticated Characterization Vehicle (CV)TM test chips, fast electrical test and Automatic Defect Localization (ADL) are critical components of the method. Advanced statistical analysis and visualization of the detected and localized electrical defects provides a comprehensive view of the yield loss mechanisms. In situations where the defects are not visible in a SEM of the structure surface, automated FIB and imaging is used to characterize the defect. The combined approach provides the required resolution to appropriately characterize parts per billion failure rates.

Identification of Process Window Limiting Structures by Design-Based Defect Binning

A new methodology is presented for identifying misprinted structures during the qualification of a new photomask. It is based on defect inspection of a focus- and exposure-modulated wafer. Instead of the traditional approach which employs repeater analysis, the new technique bins the defect locations according to the design structures where they occur and assigns them a criticality factor. This method allows for efficient data reduction and prioritization of suspect sites, leading to identification of marginally-printed structures within the patterning process window.

Accurate Litho Model Tuning Using Design-Based Defect Binning

Advanced lithography optical proximity correction (OPC) techniques rely on accurately tuned process models. Although through-process OPC models are being used for critical layers at the 65-nm node, typically an initial model is created at a single optimized process setting. Such ldquobest conditionrdquo models often produce process-window limiting structures that can impact yield. A new methodology is presented for identifying misprinted structures during the qualification of a new photomask and optimizing the process model based on those structures. Instead of the traditional approach which employs repeater analysis, the new technique bins the process-limiting structures according to their design. This method enables efficient data reduction and identification of a new feature set for lithography process model tuning.

Advanced SEM-based metrology of systematic defects

This paper describes a quantitative SEM-based inspection methodology implemented in IBMs 300 mm FAB to detect, monitor, and resolve systematic defect mechanisms at the 90 nm technology node. Two examples are described: (a) corrosion of copper interconnects at the bottom of isolated vias, leading to electrical opens, and (b) channels in the dielectric separating two metal line ends, resulting in electrical shorts. In both cases, this technique provided quantitative feedback unobtainable via conventional inspection techniques.