Rishiyur S. Nikhil

Bluespec System Verilog: efficient, correct RTL from high level specifications

Bluespec System Verilog is an EDL toolset for ASIC and FPGA design offering significantly higher productivity via a radically different approach to high-level synthesis. Many other attempts at high-level synthesis have tried to move the design language towards a more software-like specification of the behavior of the intended hardware. By means of code samples, demonstrations and measured results, we illustrate how Bluespec System Verilog, in an environment familiar to hardware designers, can significantly improve productivity without compromising generated hardware quality.

High-level synthesis: an essential ingredient for designing complex ASICs

It is common wisdom that synthesizing hardware from higher-level descriptions than Verilog incurs a performance penalty. The case study here shows that this need not be the case. If the higher-level language has suitable semantics, it is possible to synthesize hardware that is competitive with hand-written Verilog RTL. Differences in the hardware quality are dominated by architecture differences and, therefore, it is more important to explore multiple hardware architectures. This exploration is not practical without quality synthesis from higher-level languages.

Synthesis of synchronous assertions with guarded atomic actions

The SystemVerilog standard introduces SystemVerilog Assertions (SVA), a synchronous assertion package based on the temporal-logic semantics of PSL. Traditionally assertions are checked in software simulation. We introduce a method for synthesizing SVA directly into hardware modules in Bluespec SystemVerilog. This opens up new possibilities for FPGA-accelerated testbenches, hardware/software co-emulation, dynamic verification and fault-tolerance. We describe adding synthesizable assertions to a cache controller, and investigate their hardware cost.

Bluespec: A General-Purpose Approach to High-Level Synthesis Based on Parallel Atomic Transactions

Bluespec SystemVerilog (BSV) provides an approach to high-level synthesis that is general-purpose. That is, it is widely applicable across the spectrum of data- and control-oriented blocks found in modern SoCs. BSV is explicitly parallel and based on atomic transactions, the best-known tool for specifying complex concurrent behavior, which is so prevalent in SoCs. BSVs atomic transactions encompass communication protocols across module boundaries, enabling robust scaling to large systems and robust IP reuse. The timing model is smoothly refinable from initial coarse functional models to final production designs. A powerful type system, extreme parameterization, and higher-order descriptions permit a single parameterized source to generate any member of a family of microarchitectures with different performance targets (area, clock speed, power); here, too, the key enabler is the control-adaptivity arising out of atomic transactions. BSVs features enable design by refinement from executable specification to final implementation; architectural exploration with early architectural feedback; early fast executable models for software development; and a path to formal verification.

A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design

Bluespecs rule-based model of computation (MoC) for hardware concurrency has gained attention for several reasons. From its basis in term rewriting systems, rules have the property of atomicity, which improves correctness by construction, particularly in large-scale concurrency with finegrained, dynamic resource sharing (typical in complex hardware). Rule-based interface methods extend atomicity across module boundaries, have a natural transactional reading, and precisely and formally characterize resource-sharing constraints. All this can be synthesized to hardware with competitive quality. SystemC expresses concurrency with threading and events, just like RTL, where it is difficult to deal with fine-grain concurrency and resource sharing. Further, there is no systematic methodology for module composition. Thus, while SystemC is suitable for very coarse modeling and for embedded software development, its limitations make it difficult to model correct by construction hardware systems accurately. In this paper, we show how to integrate Bluespecs rule-based MoC into SystemC. We augment SystemC modules with rules and rule-based interface methods, and augment the SystemC simulation kernel with a rule execution kernel. The integration is augmentative in that a model can contain both rule-based modules (where hardware accuracy is desired) as well as core SystemC or TLM modules (for embedded software, instruction-set simulators, existing SystemC IP, or pure behavioral models), thus providing the advantages of each MoC where appropriate

Abstraction in hardware system design

Applying lessons from software languages to hardware languages using Bluespec SystemVerilog.

What is Bluespec

Bluespec refers to a language and associated tools which are being used for all aspects of hardware system design . specification, synthesis, modeling, and verification. The language, BSV (Bluespec SystemVerilog), is based on a new model of computation for hardware, where all behavior is described as a set of rewrite rules, or Guarded Atomic Actions. Unlike the process/thread model of Verilog, VHDL and SystemC, or the sequential model of C/C++, all behavior of a BSV program can be understood in terms of atomic rule firings. This computational model has a long pedigree in formal specification and verification systems (e.g., Dijkstras Guarded Commands, UNITY, TLA+, and EventB), and BSV makes it available for hardware design.

Types, Functional Programming and Atomic Transactions in Hardware Design

Most hardware design languages have not benefited from modern ideas in programming languages. We describe aspects of BSV, a recent language for designing hardware systems that makes extensive use of Haskell types (Hindley-Milner types and type classes), functional programming (higher-order functions, monads) and atomic transactions in the form of concurrent rewrite rules.

Hands-on Introduction to Bluespec System Verilog (BSV)

BSV is a modern, fully synthesizable design language in which all behavior is expressed with Guarded Atomic Actions (rewrite rules). Rules can be systematically composed from fragments across module boundaries using atomic transactional interfaces. BSV has powerful abstraction mechanisms such as expressive and polymorphic types with overloading and strong static type-checking, full orthogonality (all types are first-class), and Turing-complete static elaboration. Thus, BSV is scalable to large, industrial-strength SoCs even while designs remain highly parameterized and succinct. In this tutorial, you will get a solid technical introduction to BSV and learn how it improves many aspects of modern SoC development: modeling, early SW development, architecture exploration, design, verification, and long-term evolution and maintenance. The lectures will be organized around a few serious examples and we will examine and analyze excerpts of their actual source code. The tutorial is also hands-on: Participants who bring their laptops will receive a non-commercial but full-featured short-term installation of the latest release of BSV (native under Linux, and via a VMWare image for other OSs). During the tutorial you will work with lab exercises tied to the lecture content. After the tutorial you will be able to continue your own exploration with plenty of other examples and lab exercises.

ESL flows are enabled by high-level synthesis with universality

Due to their size and complexity, SoCs today require a “whole-system” approach to validation and verification, using real data traffic, throughout the design cycle. Instead of isolated IP verification with custom testbenches, followed by system integration, designers need to start with whole-system models in which subsystems can be independently substituted by refined models and IP blocks, so that there is a continuous system-level validation. Design languages need to be universal to express configurations that are so heterogeneous, both in the functionality and in level of abstraction. Further, they need to be universally synthesizable so that any such configuration can be run on hardware-assisted verification platforms (such as FPGAs) to achieve the speeds needed for meaningful validation and verification.