Robert A. Todd

Parallel processing approaches in RET and MDP: new hybrid multithreading and distributed technology for optimum throughput in a hierarchical flow

The continuous integration trend in design and broad deployment of resolution enhancement techniques (RET) have a tremendous impact on circuit file size and pattern complexity. Increasing design cycle time has drawn attention to the data manipulation steps that follow the physical layout of the design. The contributions to the total turn-around time for a design are twofold: the time to get the data ready for the hand-off to the mask writer is growing, but also the time it takes to write the mask is heavily influenced by the size and complexity of the data. In order to reduce the time that is required for the application of RET and the export of the data to mask writer formats, massively parallel processing approaches have been described. This paper presents such computing algorithms for the hierarchical implementation of RET and mask data preparation (MDP). We focus on the parallel and flexible deployment of a new hybrid multithreaded and distributed processing scheme in homogeneous and heterogeneous computer networks called MTFlex. We describe the new methodology and discuss corresponding hardware and software configurations. The application of this “MTFlex” computing scheme to different tasks in post-tapeout data preparation is shown in examples.

Geometric Pattern Match Using Edge Driven Dissected Rectangles and Vector Space

In this paper, we propose novel algorithms for pattern matching which dissects patterns into rectangles based on polygon edges. Unlike other design rule check (DRC)-based pattern matching algorithms, our solution utilizes simple DRC edge length rules to create rectangles for hotspot pattern descriptions. This approach has at least three advantages over other solutions. First, it is faster than other state-of-the-art pattern matching tools. Second, it is intuitive and simple for pattern matching engineers to understand and describe patterns. Third, it scales well for parallel computation. We also show how to improve pattern matching run time using vector space created by an origin rectangle and other reference rectangles inside a pattern bounding box. By adopting the vector concept, we iterate only once or twice when detecting different pattern orientations. Other pattern matching techniques usually iterate eight times (4 rotations × 2 mirrored images) to detect all of the eight different orientations. Our method eliminates these unnecessary iterations.

Architecting for Physical Verification Performance and Scaling

The primary goal when using physical verification tools is to achieve the best performance at the lowest cost, both in resources and time. Physical verification tools rely on multiple enabling technologies to contribute to runtime and turnaround time reduction. Using differing combinations of architecture and scaling, this paper compares and contrasts three physical verification approaches to determine the combination of factors most likely to produce the desired results in a production environment.