Emile Sahouria

Integration of optical proximity correction strategies in strong phase shifters design for poly-gate layers

In this paper we discuss some of the problems and solutions discovered when implementing 2-mask strong phase shifter designs for the poly gate level in logic designs. Experimental results are presented showing pattern fidelity for different reticle designs. Simulations are presented indicating the improvement in pattern fidelity that can be expected from using OPC. Simulations, PSM assignment and model-based OPC correction are performed by the Calibre WORKbench, Calibre DRC, Calibre PSMgate and Calibre OPCpro tools from Mentor Graphics. In conclusion, we show that while fairly simple designs can be used to achieve 250 nm design rules (approximately 150 nm gates), in order to achieve both pattern fidelity as well as small feature size it is necessary to use 3-layer/phase-aware model-based OPC to correct for pattern distortion for design rules of 180 nm and below (approximately 100 nm phase-shifted gates).

CD variation analysis technique and its application to the study of PSM mask misalignment

We study the influence of process parameters on strong phase shifted and binary mask designs. The impact of a poly gate alternate phase shifting technique on CD control is analyzed for a microprocessor design. A combination of OPC and PSM tools are used to assess sensitivity of CD to the variations of defocus, exposure dose, and mask misalignment, with and without PSM. A simulation region of 640x310 microns with 20000 MOSFETs is cut out from a random logic design. The edge placement error measurement sites are assigned each 200 nm across the transistor channels to fine-monitor CD variations. Four additional measurement sites are put close to the channel ends to monitor these regions susceptible to the CD variation. We use fast simulation technique that employs optical SOCS (Sum of Coherent Systems) decomposition and Extended Variable Threshold model. Optical parameters settings are chosen to be different for the binary and PSM masks to ensure comparable CD distributions in the center of the process windows. The PSM design is a 2-mask strong phase shifter design for poly gate level. Model-based OPC is applied to all relevant layers of the design including trim masks. To explore exposure-dose-misalignment input parameter space we setup partial factorial DOE with more than 100 runs each resulting in an EPE distribution for a parameter combination. We analyzed EPE shift and EPE dispersion. A definition of an EPE-based process window is proposed to capture the “proximity signature” of the design and its dependence on the process parameters. Comparison of binary and PSM designs yielded reliable quantitative measures of the PSM design performance gain.

Phase aware proximity correction for advanced masks

In this paper we describe the use of sparse aerial image simulation coupled with process simulation, using the variable threshold resist (VTR) model, to do optical and process proximity correction (OPC) on phase shift masks (PSM). We will describe the OPC of PSM, including attenuated PSM, clear field PSM, and double exposure PSM. We will explain the method used to perform such OPC and show examples of critical dimension control improvements generated from such a technique. Simulations, PSM assignment and model based OPC corrections are performed with Calibre Workbench, Calibre DRC, Calibre PSMgate and Calibre OPCpro tools from Mentor Graphics. In conclusion we will show that PSM techniques need to be corrected by a phase aware proximity correction tool in order to achieve both pattern fidelity as well as small feature size on the wafer in a production environment.

Double-patterning decomposition, design compliance, and verification algorithms at 32nm hp

Double patterning (DP) technology is one of the main candidates for RET of critical layers at 32nm hp. DP technology is a strong RET technique that must be considered throughout the IC design and post tapeout flows. We present a complete DP technology strategy including a DRC/DFM component, physical synthesis support and mask synthesis. In particular, the methodology contains: - A DRC-like layout DP compliance and design verification functions; - A parameterization scheme that codifies manufacturing knowledge and capability; - Judicious use of physical effect simulation to improve double-patterning quality; - An efficient, high capacity mask synthesis function for post-tapeout processing; - A verification function to determine the correctness and qualify of a DP solution; Double patterning technology requires decomposition of the design to relax the pitch and effectively allows processing with k1 factors smaller than the theoretical Rayleigh limit of 0.25. The traditional DP processes Litho-Etch-Litho- Etch (LELE) [1] requires an additional develop and etch step, which eliminates the resolution degradation which occurs in multiple exposure processed in the same resist layer. The theoretical k1 for a double-patterning technology applied to a 32nm half-pitch design using a 1.35NA 193nm imaging system is 0.44, whereas the k1 for a single-patterning of this same design would be 0.22 [2], which is sub-resolution. This paper demonstrates the methods developed at Mentor Graphics for double patterning design compliance and decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. It also demonstrates verification solution implementation in the chip design flow and post-tapeout flow.

Fully automatic side lobe detection and correction technique for attenuated phase-shift masks

Using a new functionality of the Calibre PrintImage tool, a method for side lobe correction is presented. A full chip aerial image mapping is first obtained and then analyzed to detect and output polygons corresponding to chip areas where the aerial image intensity is above a user set threshold. Using state of the art DRC tool and associated RET software from Mentor Graphics we are able to propose a completely automated flow for side lobe detection and correction. Mask manufacturing complexity can also be taken into consideration using geometrical constraints similar to those used for scattering bars, such as minimum length, minimum width and minimum space to main features.

Phase and transmission errors aware OPC solution for PSM: feasability demonstration

To follow the SIA roadmap, lithographers must deal everyday with the bad effects of a low-kl lithography transfer process. One of the ways to reduce the pressure associated with such low-kl values is to use Alternating Phase Shift Masks (henceforth “Alt-PSM”). Unfortunately, Alt-PSM also has some drawbacks, such as transmission imbalance between the phase shifted and non-phase shifted areas, and aspect ratio phase etch depth variation resulting from the mask etching process. Moreover, fast two-dimensional simulators that are commonly used in resolution enhancement simulation are unable to directly predict these inherently three-dimensional effects. We demonstrate a general approach to simulate and correct these effects in large circuit designs by combining accurate mask representation with Optical and Process Correction (“OPC”). Using a DRC tool, geometry in the input circuit design is partitioned based on size and shape. Guided by accurate three-dimensional simulations or empirical data, these partitions may be classified and assigned different phases and transmission values to more realistically simulate the mask. By using this more accurate mask representation in our integrated OPC tool, Calibre OPCPro, we are able to correct designs for these three-dimensional mask effects as well as for conventional proximity effects.

Assessment and comparison of different approaches for mask write time reduction

The extension of 193nm exposure wavelength to smaller nodes continues the trend of increased data complexity and subsequently longer mask writing times. We review the data preparation steps post tapeout, how they influence shot count as the main driver for mask writing time and techniques to reduce that impact. The paper discusses the application of resolution enhancements and layout simplification techniques; the fracture step and optimization methods; mask writing and novel ideas for shot count reduction. The paper will describe and compare the following techniques: optimized fracture, pre-fracture jog alignment, generalization of shot definition (L-shot), multi-resolution writing, optimized-based fracture, and optimized OPC output. The comparison of shot count reduction techniques will consider the impact of changes to the current state of the art using the following criteria: computational effort, CD control on the mask, mask rule compliance for manufacturing and inspection, and the software and hardware changes required to achieve the mask write time reduction. The paper will introduce the concepts and present some data preparation results based on process correction and fracturing tools.

Reducing shot count through optimization-based fracture

The increasing complexity of RET solutions with each new process node has increased the shot count of advanced photomasks. In particular, the introduction of inverse lithography masks represents a significant increase in mask complexity. Although shot count reduction can be achieved through careful management of the upstream OPC strategy and improvement of fracture algorithms, it is also important to consider more dramatic departures from traditional fracture techniques. Optimization based fracture allows for overlapping shots to be placed in a manner that allows the mask intent to be realized while achieving significant savings in shot count relative to traditional fracture based methods. We investigate the application of Optimization based fracture to reduce the shot count of inverse lithography masks, provide an assessment of the potential shot count savings, and assess its impact on lithography process window performance.

Pattern based mask process correction: impact on data quality and mask writing time

The continuous drive of the semiconductor industry towards smaller features sizes requires mask manufacturers to achieve ever tighter tolerances for the most critical dimensions on the mask. CD uniformity requires particularly tight control. Equipment manufacturers and process engineers target their development to support these requirements. But as numerous publications indicate, more sophisticated data correction methods are still employed to compensate for shortcomings in equipment and process or to account for the boundary conditions in some layouts that contribute to process deviations. Among the corrected effects are proximity and linearity effects, fogging and etch effects, and pattern fidelity. Different designs vary by pattern size distribution as well as by pattern density distribution. As the implementation of corrections for optical proximity effects in wafer lithography has shown, breaking up the original polygons in the design layout for selective and environment-aware correction yields increased data volumes and can have an impact on the data quality of the mask writing data. The paper investigates the effect of various correction algorithms specifically deployed for mask process effects on top of wafer process related corrections. The impact of MPC flows such as rule-based linearity and proximity correction and density-based long range effect correction on the metrics for data preparation and mask making is analyzed. Experimental data on file size, shot count and data quality indicators including small figure counts are presented for different correction approaches and a variety of correction parameters.

Full-chip-model-based correction of flare-induced linewidth variation

Scattered light in optical lithography, also known as flare, has been shown to cause potentially significant linewidth variation at low-k1 values. The interaction radius of this effect can extend essentially from zero to the full range of a product die and beyond. Because of this large interaction radius the correction of the effect can be very computation-intensive. In this paper, we will present the results of our work to characterize the flare effect for 65nm and 90nm poly processes, model that flare effect as a summation of gaussian convolution kernels, and correct it within a hierarchical model based OPC engine. Novel methods for model based correction of the flare effect, which preserve much of the design hierarchy, is discussed. The same technique has demonstrated the ability to correct for long-range loading effects encountered during the manufacture of reticles.