Robert C. Cole

Integrated TiC coatings for moving MEMS

The application of wear-resistant coatings to microelectromechanical systems (MEMS) devices offers the potential of addressing the reliability of moving MEMS devices. However, coating non-line-of-sight, concealed surfaces in fully released 3D MEMS structures, especially those behind micron-sized apertures, is a difficult problem to overcome with most deposition techniques. A practical and viable solution to this problem is the direct integration of wear-resistant coatings into the MEMS fabrication process. Using this approach we have inserted pulsed-laser-deposited titanium carbide (TiC) coatings between critical polysilicon interfaces during fabrication of a MEMS device. This paper describes the details of inserting laser-ablated TiC coatings into a user-friendly surface micromachining process for MEMS to protect key sliding Si surfaces in MEMS motors. This hybrid technology is an effective way of inserting wear-resistant coatings such as TiC into the MEMS fabrication scheme.

Determination of back interface state distribution in fully depleted SOI MOSFETs

Two experimental techniques are proposed to extract the back interface state energy distribution of a silicon-on-insulator (SOI) film from the terminal characteristics of a fully depleted SOI MOSFET. The observed dependences of the MOSFET threshold voltage and subthreshold slope on substrate voltage are used to determine the density of back interface states (D/sub itb/) as a function of position in the bandgap. Data from fully depleted SIMOX n- and p-MOSFETs yield distributions of D/sub itb/ ranging from a high of approximately 10/sup 12/ cm/sup -2/ eV/sup -1/ near the n- and p-Fermi levels and decreasing below 10/sup 11/ cm/sup -2/ eV/sup -1/ near midgap.<<ETX>>

Determination of back interface state distribution in fully-depleted SOI MOSFETs

Two techniques based on observable DC MOSFET device parameters are described that can be used to extract the interface state density at the back Si-SiO/sub 2/ interface as a function of position in the bandgap. These techniques can be incorporated into a DC MOSFET test program. A set of I/sub D/-V/sub GS/ curves is shown for a thin (200 nm, type 1) fully depleted SIMOX (separation by implanted oxygen) p/sup +/-poly-gate n-MOSFET as substrate bias varies from -15 to 0 V. Over this substrate voltage range, the back interface passes from accumulation through depletion into inversion. Also shown is the extracted distribution of back interface states below midgap as determined from both the threshold and subthreshold slope data from this n-MOSFET.<<ETX>>

Modified quantum-well infrared photodetector designs for high-temperature and long-wavelength operation

A principal concern with the performance of GaAs/AlGaAs multiple quantum well long- wavelength detectors is obtaining high detectivity at relatively high temperatures. We have fabricated GaAs/AlGaAs quantum well infrared photodetectors (QWIPs) with graded barrier regions by varying the aluminum concentration during the barrier growth to improve high temperature performance. The effect of barrier grading has been characterized by the measurement of dark current and responsivity, leading to an evaluation of the temperature dependent detectivity. Detectivity of 2 X 109 cm(root)Hz/W at 100 K has been measured on graded barrier QWIPs. We also report on the investigation of QWIPs with cut- off wavelengths ((lambda) c) greater than 12 micrometers . A QWIP with (lambda) c approximately 13.8 micrometers was grown with peak responsivity (Rp) of 1.2 A/W at 10 K. Both Rp and (lambda) c were weakly bias dependent. The maximum detectivity of 6 X 1012 cm(root)Hz/W was at 10 K at 11.7 micrometers and (lambda) c equals 14.5 micrometers .

Pulsed-laser deposited TiC coatings for MEMS

Titanium carbide (TiC) thin films have very desirable properties that make them ideally suited for applications to MEMS devices. TiC has been one of the preferred coatings for improving the performance of macroscopic moving mechanical components due to its established wear-resistance. Pulsed laser deposition (PLD) has been an excellent method for the deposition of TiC because unlike any other deposition process for TiC, PLD offers the capability of producing high-quality films even at room-temperature. Using a patented PLD technique, especially designed and optimized for the deposition of high-hardness, particulate-free films, we have deposited TiC coatings on a variety of surfaces, including Si and several MEMS compatible film-layers. Our results have demonstrated that TiC coatings also offer a high wear-resistance to Si surfaces. This, together with the excellent chemical and mechanical properties, and thermal stability of our PLD TiC coatings, has led to our application of TiC to moving MEMS devices fabricated from Si. The fabrication of Si MEMS devices is quite well established, however, the reliability and performance of MEMS devices such as microgears, micromotors and microactuators, which involve sliding Si surfaces, remain an open question. The short functional life of these devices is attributed to the excessive wear rate of Si induced by high friction. The work presented here describes a hybrid process whereby PLD is used in conjunction with the Aerospace MEMS fabrication process (AIMMOS) for inserting TiC coatings into critical interfaces in MEMS devices that would involve sliding contact between two Si surfaces. The PLD of TiC, the spectroscopy of the plume, and the properties and applications of PLD-TiC for MEMS will be discussed.

Development of released micromachined structures for millimeterwave device applications: preliminary results

The exploding interest in miniaturized subsystems for mobile and satellite communications applications has revealed a dire need for higher levels of integration, performance, and cost-effectiveness from millimeter-wave components. Monolithic microwave integrated circuit (MMIC) technology has enabled tremendous strides in efforts to miniaturize analog communications circuits and deliver advanced performance at the higher, less-crowded millimeter-wave frequency regime. Similarly, microelectromechanical systems (MEMS) technologies have realized their own successes in the likes of accelerometers for air-bag deployment systems and miniaturized motors. The strengths of MMICs and MEMS, two areas whose applications have largely developed independently, can now be synthesized to yield the types of components that will deliver the high performance, space efficiency, and low cost demanded by the current communications technology needs. This paper reports preliminary progress in the development of released surface-micromachined structures suitable for use in such millimeter-wave device applications. Several experimental structures are described, with a brief overview of the fabrication process used and the eventual millimeter-wave circuit context for the structures.

Formation of a bonded SOI interface using a spin-on dielectric

The formation of a bonded interface between thermally oxidized silicon wafers forms the basis for the bond-and-etchback SOI (BESOI) technology. Conventional bonding approaches require a high degree of planarity over the wafer surfaces. Significant nonplanarity caused by particles or other defects on the wafer surfaces can result in substantial yield loss during the bonding process. Furthermore, the bond-and-etchback technique might be extendable to a Gate-All-Around SOI process if the buried polysilicon gate could be patterned before the bonding step. However, the non-planarity of the wafer resulting from the definition of the buried polysilicon gate would prevent bonding this wafer to an unpatterned wafer via the conventional bond-and-etchback approach. We describe an approach to wafer bonding that includes the formation of a spin-on dielectric on one or both of the wafer surfaces. This spin-on glass has the advantage that it can subsume defects on the wafer surfaces resulting in a high degree of planarity even over particles as large as the film thickness when boron and/or phosphorus are incorporated into the glass and a thermal reflow step is included.

X-ray, XTEM and RBS analysis of recrystallized ion beam amorphized CVD Si

Ion beam modification of materials has been used for the formation of high quality single-crystal silicon (c-Si) over oxide, for high speed CMOS device applications. In the lateral solid phase epitaxy (LSPE) technique, thin c-Si layers (typically 300 nm) are formed by ion beam amorphization of a low pressure chemical vapor deposited (LPCVD) polysilicon layer over an oxidized Si wafer in which seed windows have been opened in the oxide. A c-Si layer is formed by LSPE from the single-crystal substrate up and over the thermal oxide adjacent to the oxide window for distances of up to 4 μm beyond the window boundary. We have obtained high quality 〈100〉 single-crystal silicon by conversion of polycrystalline LPCVD-Si, using rapid thermal annealing (RTA) followed by ion implantation amorphization and subsequent thermal recrystallization. Amorphization of LPCVD deposited poly-Si to a depth of 300 nm is achieved by LN2 temperature implants of 5 × 1014 cm−228Si+ at 80 and 230 keV each. The crystallinity upon thermally induced recrystallization is evaluated by X-ray rocking curves, X-ray Read camera, RBS and cross-sectional transmission electron muscopy (XTEM).