Ronald C. Lacoe

Application of hardness-by-design methodology to radiation-tolerant ASIC technologies

Radiation-hard ASIC design is enabled by the trend in commercial microelectronics toward increased radiation hardness, demonstrated here with new radiation results on a 0.25-/spl mu/m commercial process utilizing shallow trench isolation. A design comparison is made between creating ASICs targeting a traditional rad-hard foundry, which may be more than two generations behind commercial foundries, applying hardness-by-design methodology at a commercial foundry, and directly targeting a commercial foundry using commercial design practices.

Improving Integrated Circuit Performance Through the Application of Hardness-by-Design Methodology

Increased space system performance is enabled by access to high-performance, low-power radiation-hardened microelectronic components. While high performance can be achieved using commercial CMOS foundries, it is necessary to mitigate radiation effects. This paper describes approaches to fabricating radiation-hardened components at commercial CMOS foundries by the application of novel design techniques at the transistor level, the cell level, and at the system level. This approach is referred to as hardness-by-design. In addition, trends in the intrinsic radiation hardness of commercial CMOS processes will be discussed.

Total dose hardness of three commercial CMOS microelectronics foundries

We have measured the effects of total ionizing dose (TID) on CMOS FETs, ring oscillators and field-oxide transistor test structures fabricated at three different commercial foundries with four different processes. The foundries spanned a range of integration levels and included Hewlett-Packard (HP) 0.5 /spl mu/m and 0.8 /spl mu/m processes, an Orbit 1.2 /spl mu/m process, and an AMI 1.6 /spl mu/m process. We found that the highest tolerance to TID was for the HP 0.5 /spl mu/m process, where the shift in NMOS threshold voltage was less than 40 mV at 300 krad. An examination of the dependence of the threshold voltage shift on gate oxide thickness indicated that oxides of the different commercial processes were of similar quality, and that the improvement in the total dose tolerance of the HP 0.5 /spl mu/m technology is associated with the scaling of the gate oxide. Measurements on field-oxide transistors from the HP 0.5 /spl mu/m process were shown not to invert for signal voltages at 300 krad, maintaining the integrity of the LOCOS isolation. The impact of these results is, discussed in terms of the potential insertion of commercial microelectronics into space systems.

New understanding of LDD CMOS hot-carrier degradation and device lifetime at cryogenic temperatures

This work shows that the worst-case gate voltage stress condition for LDD nMOSFETs is a strong function of the channel length, drain voltage, and operating temperature. A new cross-over behavior of the worst-case gate voltage condition is reported at low temperatures. New understanding of the hot-carrier mechanisms at low temperatures is also discussed. Low temperature effects such as freeze-out are shown to have important contributions to the hot-carrier behavior at low temperatures. A trend is identified for the first time which suggests important consequences for the hot-carrier reliability of deep sub-micron channel length MOSFETs under normal operating temperatures.

Angular Dependence of Single Event Sensitivity in Hardened Flip/Flop Designs

SEU data on 90 nm structures displays a strong dependence on incident angle. A right parallelepiped (RPP) approximation is clearly not applicable to the observed response. This paper presents the data, possible mechanisms, and implications for testing and error rate predictions.

Reliability enhancement in high-performance MOSFETs by annular transistor design

The use of annular MOSFET design, which has demonstrated total-dose radiation immunity in CMOS circuits, can improve the hot-carrier reliability of CMOS circuits by reducing the drain electric field compared to conventionally designed MOSFETs. A theoretical analysis of the annular n-MOSFET in saturation verifies the reduction of the drain electric field in properly designed MOSFETs. Hot-carrier data for an enclosed 0.25-/spl mu/m n-MOSFET demonstrate an improvement in hot-carrier lifetime by more than 3x compared to a conventional device in the same technology.

Implications of radiation-induced dopant deactivation for npn bipolar junction transistors

Metal-oxide-silicon capacitors fabricated in a bipolar process were examined for densities of oxide trapped charge, interface traps and deactivated substrate acceptors following high-dose-rate irradiation at 100/spl deg/C. Acceptor neutralization near the Si surface occurs most efficiently for small irradiation biases in depletion. The bias dependence is consistent with compensation and passivation mechanisms involving the drift of H/sup +/ ions in the oxide and Si layers and the availability of holes in the Si depletion region. The capacitor data were used to simulate the impact of acceptor neutralization on the current gain of an irradiated npn bipolar transistor. Neutralized accepters near the base surface enhance current gain degradation associated with radiation-induced oxide trapped charge and interface traps by increasing base recombination. The additional recombination results from the convergence of carrier concentrations in the base and increased sensitivity of the base to oxide trapped charge. The enhanced gain degradation is moderated by increased electron injection from the emitter. These results suggest that acceptor neutralization may complicate hardness assurance test methods for linear circuits, which are based on elevated temperature irradiations.

Geometric component of charge pumping current in nMOSFETs due to low-temperature irradiation

The geometric component of charge pumping current was examined in n-channel metal-oxide-silicon field effect transistors (MOSFETs) following low-temperature irradiation. In addition to the usual dependencies on channel length and gate bias transition time, the geometric component was found to increase with radiation-induced oxide-trapped charge density and decreasing temperature. A postirradiation injection of electrons into the gate oxide reduces the geometric component along with the density of oxide-trapped charge, which clearly demonstrates that the two are correlated. A fit of the injection data to a first-order model for trapping kinetics indicates that the electron trapping occurs predominantly at a single type of Coulomb-attractive trap site. The geometric component results primarily from the bulk recombination of channel electrons that fail to transport to the source or drain during the transition from inversion to accumulation. The radiation response of these transistors suggests that Coulomb scattering by oxide-trapped charge increases the bulk recombination at low temperatures by impeding electron transport. These results imply that the geometric component must be properly accounted for when charge pumping irradiated n-channel MOSFETs at low temperatures.

Charge separation technique for metal-oxide-silicon capacitors in the presence of hydrogen deactivated dopants

An improved charge separation technique for metal-oxide-silicon (MOS) capacitors is presented which accounts for the deactivation of substrate dopants by hydrogen at elevated irradiation temperatures or small irradiation biases. Using high-frequency capacitance-voltage (C-V) measurements, radiation-induced inversion voltage shifts are separated into components due to oxide trapped charge, interface traps and deactivated dopants, where the latter is computed from a reduction in Si capacitance. In the limit of no radiation-induced dopant deactivation, this approach reduces to the standard midgap charge separation technique used widely for the analysis of room-temperature irradiations. The technique is demonstrated on a p-type MOS capacitor irradiated with {sup 60}Co {gamma}-rays at 100 C and zero bias, where the dopant deactivation is significant.

Wavelength dependence of transient laser-induced latchup in epi-CMOS test structures

We report the thresholds for laser-induced latchup on epitaxial CMOS test structures for 600 nm and 815 nm excitation. We analyze the differences observed in terms of different latchup triggering mechanisms and compare the results with measurements of energetic particle-induced latchup.