Robert C. Zak

The Network Architecture of the Connection Machine CM-5

The Connection Machine Model CM-5 Supercomputer is a massively parallel computer system designed to offer performance in the range of 1 teraflops (1012floating-point operations per second). The CM-5 obtains its high performance while offering ease of programming, flexibility, and reliability. The machine contains three communication networks: a data network, a control network, and a diagnostic network. This paper describes the organization of these three networks and how they contribute to the design goals of the CM-5.

The network architecture of the Connection Machine CM-5 (extended abstract)

The Connection Machine Model CM-5 Supercomputer is a massively parallel computer system designed to offer performance in the range of 1 teraflops (1012 floating-point operations per second). The CM-5 obtains its high performance while offering ease of programming, flexibility, and reliability. The machine contains three communication networks: a data network, a control network, and a diagnostic network. This paper describes the organization of these three networks and how they contribute to the design goals of the CM-5.

SMP System Interconnect Instrumentation for Performance Analysis

The system interconnect is often the performance bottleneck in SMP computers. Although modern SMPs include event counters on processors and interconnects, these provide limited information about the interaction of processors vying for shared resources. Additionally, transaction sources and addresses are not readily available, making analysis of access patterns and data locality difficult. Enhanced system interconnect instrumentation is required to extract this information. This paper describes instrumentation implemented for monitoring the system interconnect on Sun Fire™ servers. The instrumentation supports sophisticated programmable filtering of event counters, allowing us to construct histograms of system interconnect activity, and a FIFO to capture trace sequences. Our implementation results in a very small hardware footprint, making it appropriate for inclusion in commodity hardware. We also describe a sampling of software tools and results based on this infrastructure. Applications have included performance profiling, architectural studies, and hardware bringup and debugging.

An IEEE 1149.1 compliant testability architecture with internal scan

A testability architecture for VLSI devices which is IEEE 1149.1 compliant and includes extensions for partitionable internal scan chains is described. The architecture includes a fully synchronous scan cell library and an explicit synchronization barrier between test clock synchronous logic and system clock synchronous logic. The explicit synchronization barrier guarantees coherent sampling of device state. These techniques result in VLSI designs that are amenable to static timing analysis and are extensible to at-speed built-in-self-test (BIST). Results for five VLSI devices used in the CM5, a massively parallel supercomputer, show low logic overhead (8-20%) and high in-system stuck-at fault coverage (>99.5%).<<ETX>>

Set-associative dynamic random access memory

Static-column dynamic RAMs (random-access memories) offer fast access to successive locations within a single row, a fact which has been used in their implementation in fast cacheless memory systems. Such caches are necessarily nonassociative (direct-mapped), limiting their performance relative to set-associative caches of similar total capacity. The authors describe an architecture for dynamic RAM chips which circumvents this limitation by providing several alternative static row buffers on each chip. Cacheless memory systems utilizing these devices are able to achieve the performance characteristics of relatively expensive set-associative cached memories using only economical high-density RAM parts. Simulation results on set-associate dynamic RAMs (SADRAMs) are presented and some plausible roles for SADRAMs in various architectural contexts are noted.<<ETX>>