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Featured researches published by Shaw-Wen Yang.


Journal of Parallel and Distributed Computing | 1996

The Network Architecture of the Connection Machine CM-5

Charles E. Leiserson; Zahi S. Abuhamdeh; David C. Douglas; Carl R. Feynman; Mahesh N. Ganmukhi; Jeffrey V. Hill; W. Daniel Hillis; Bradley C. Kuszmaul; Margaret A. St. Pierre; David S. Wells; Monica C. Wong-Chan; Shaw-Wen Yang; Robert C. Zak

The Connection Machine Model CM-5 Supercomputer is a massively parallel computer system designed to offer performance in the range of 1 teraflops (1012floating-point operations per second). The CM-5 obtains its high performance while offering ease of programming, flexibility, and reliability. The machine contains three communication networks: a data network, a control network, and a diagnostic network. This paper describes the organization of these three networks and how they contribute to the design goals of the CM-5.


acm symposium on parallel algorithms and architectures | 1992

The network architecture of the Connection Machine CM-5 (extended abstract)

Charles E. Leiserson; Zahi S. Abuhamdeh; David C. Douglas; Carl R. Feynman; Mahesh N. Ganmukhi; Jeffrey V. Hill; W. Daniel Hillis; Bradley C. Kuszmaul; Margaret A. St. Pierre; David S. Wells; Monica C. Wong; Shaw-Wen Yang; Robert C. Zak

The Connection Machine Model CM-5 Supercomputer is a massively parallel computer system designed to offer performance in the range of 1 teraflops (1012 floating-point operations per second). The CM-5 obtains its high performance while offering ease of programming, flexibility, and reliability. The machine contains three communication networks: a data network, a control network, and a diagnostic network. This paper describes the organization of these three networks and how they contribute to the design goals of the CM-5.


international conference on computer design | 1992

Functional VLSI design verification methodology for the CM-5 massively parallel supercomputer

M. St. Pierre; Shaw-Wen Yang; Daniel R. Cassiday

The methodology and techniques developed from the functional verification of five of the VLSI chips used in the CM-5, a massively parallel supercomputer, are described. The verification methodology uses multiple layers of abstraction and concurrent development of design and test to reduce overall development time and increase the effectiveness and coverage of the functional tests. Some of the pragmatic techniques proved useful include continuous monitoring of all interfaces and finite-state machines (FSMs), and demons to exercise the chip in difficult-to-reach states.<<ETX>>


Archive | 1991

Digital clock buffer circuit providing controllable delay

W. Daniel Hillis; Zahi S. Abuhamdeh; Bradley C. Kuszmaul; Jon P Wade; Shaw-Wen Yang


Archive | 1996

Massively parallel computer including auxiliary vector processor

Jon P. Wade; Daniel R. Cassiday; Robert D. Lordi; Guy L. Steele; Margaret A. St. Pierre; Monica C. Wong-Chan; Zahi S. Abuhamdeh; David C. Douglas; Mahesh N. Ganmukhi; Jeffrey V. Hill; W. Daniel Hillis; Scott J. Smith; Shaw-Wen Yang; Robert C. Zak


Archive | 1991

Parallel computer system

David C. Douglas; Mahesh N. Ganmukhi; Jeffrey V. Hill; W. Daniel Hillis; Bradley C. Kuszmaul; Charles E. Leiserson; David S. Wells; Monica C. Wong; Shaw-Wen Yang; Robert C. Zak


Archive | 1993

Parallel computer system including arrangement for transferring messages from a source processor to selected ones of a plurality of destination processors and combining responses

Robert C. Zak; Charles E. Leiserson; Bradley C. Kuzmaul; Shaw-Wen Yang; W. Daniel Hillis; David C. Douglas; David Potter


Archive | 1996

Multiprocessing system configured to perform synchronization operations

Erik Hagersten; Robert C. Zak; Shaw-Wen Yang; Aleksandr Guzovskiy; William A. Nesheim; Monica C. Wong-Chan; Hien R. Nguyen


Archive | 1994

Router for parallel computer including arrangement for redirecting messages

David C. Douglas; Charles E. Leiserson; Bradley C. Kuszmaul; Shaw-Wen Yang; W. Daniel Hillis; David S. Wells; Carl R. Feynman; Bruce J. Walker; Brewster Kahle


Archive | 1994

Parallel computer system including arrangement for quickly draining messages from message router

Bradley C. Kuszmaul; Charles E. Leiserson; Shaw-Wen Yang; Carl R. Feynman; W. Daniel Hillis; David S. Wells; Cynthia J. Spiller

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Bradley C. Kuszmaul

Massachusetts Institute of Technology

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Charles E. Leiserson

Massachusetts Institute of Technology

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