Robert D. Sandell

High data rate switch with amplifier chip

A critical component for high bandwidth communications links is a digital switch. Desirable features of a digital switch include: high input/output bandwidth, high channel count, scalability, low latency and interchannel skew. Superconductive circuits, with simultaneous high speed and low power advantages (even including the requisite cryocooler) have been applied to a highly scaleable crossbar switch, useful in supercomputer networks, massively parallel processing (MPP), and high data rate telecommunications. We report here on the testing of a 16/spl times/16 switch chip based on the switch chip component of the highly scaleable crossbar system. We have successfully transmitted multi-Gb/s data through this superconducting switch, with packet destination addressing decoded from the header of the data packet. The data are transmitted to a separate superconducting amplifier chip, mounted on a superconducting multi-chip module with the switch. The switch is a crossbar architecture, voltage state design, and operated to beyond 3 Gb/s. The amplifier is a clocked latching stack of Josephson junctions. Output of the amplifier at 6.2 Gb/s is 7.0 mV, which facilitates the interface of the module to its users. BER of the two-chip assembly is 10/sup -9/ or less above 2 Gb/s.

Multi-chip packaging for high speed superconducting circuits

We report the development of a multi-chip module (MCM) technology using Nb metallization and benzocyclobutene (BCB) polymer dielectric. The Nb/BCB structure displays very low loss, has low processing temperature, and forms a wide range of microstrip transmission line impedances. We are developing flip chip, solder attachment for die mounting. We also report the electrical characterization of Nb/BCB/Nb for both microstrip resonators, delay lines, and bandpass filters.<<ETX>>

Error rate measurements of a Josephson single flux quantum binary ripple counter

Single-flux quantum devices are used in superconductive analog-to-digital converters (ADCs), shift registers, and memory cells. They have been proposed for logic applications. The authors report the performance of high-speed superconducting, single-flux quantum (SFQ) ripple counters. Both memory and logic functions of the counter are investigated. Errors in logic operation produce bit error rates (BERs) as low as 0.22 errors per million binary operations, measured while counting 100-MHz pseudorandom input pulses. Errors in memory function do not occur on the time scale of the measurements. The BER is shown to be nearly independent of input bit rate and pattern, but strongly dependent on the counter cell operating point.<<ETX>>

Design of a 10 K NbN A/D converter for IR focal plane array sensors

We are implementing a 12 bit SFQ counting ADC with parallel-to-serial readout using our established 10 K NbN capability. This circuit provides a key element of the analog signal processor (ASP) used in large infrared focal plane arrays. The circuit processes the signal data stream from a Si:As BIB detector array. A 10 mega samples per second (MSPS) pixel data stream flows from the chip at a 120 megabit bit rate in a format that is compatible with other superconductive time dependent processor (TDP) circuits being developed. We will discuss our planned ASP demonstration, the circuit design, and test results.<<ETX>>

Multi-Gb/s operation of flipped chip MVTL circuits

Development of a reliable flipped chip mounting technique enables demonstration of high speed, complex digital circuits. Flip chip mounting has greatly reduced parasitic inductance compared to conventional wire bonding, and permits remounting of known good die onto multi-chip modules. Superconductive digital circuits have operated to 4.3 Gb/s in our custom test station. The circuit and carrier are fabricated using TRWs foundry process. The chips are flipped onto a superconducting coplanar carrier using a low temperature solder reflow process reported on at this conference. Testing is performed in a multi-GHz, flip contact, variable temperature probe. This test facility is capable of testing circuits to 12 Gb/s. We will describe the operation and performance of our circuits at high bit rates, and design improvements intended to facilitate operation at higher bit rates with improved yield. In addition, we will discuss the use of a logic simulation tool to analyze the output words, and pinpoint the gate or gates that failed to operate properly.

An SFQ digital to analog converter

We have developed and demonstrated a digital to analog converter DAC which uses an SFQ counter to precisely divide an input reference oscillator to produce a set of binary frequencies/voltages. The binary input gates the output SFQ pulses of the counter flip flops to a passive summing network, producing an analog output current. The DAC is asynchronous (no clock to reset latching circuits), low power, and requires only N equal matched resistors. We have built and tested a 4-bit Nb DAC with data clocking rates up to 1 GHz. Using the DAC we have generated arbitrary wave forms including ramps and sine waves. By measuring the harmonic content of sine wave outputs, we deduce values for the DAC linearity.

Superconductive digital readout for IR FPA sensors

We have built and demonstrated an all superconductive digital readout for use in an IR focal plane array sensor. High performance, ultralow power superconductive circuits perform the functions of low noise preamplification and analog to digital conversion. The superconductive readout was tested with a variety of detectors, including InSb, Si:As, and a thin film NbN superconducting detector. Light sources included a HeNe laser (0.6 micron), a CO2 laser (10 microns), and a blackbody (400 to 900 K). In each case, the detector and readout circuitry was assembled into a 2 inch diameter, 6 inch long test package cooled in a single dewar. We demonstrated the functionality of the detector/readout channel from input photons to output digital signal. The superconductive readout reported here used Nb-based circuits operating at 4 K. An NbN squid amplifier and detector have subsequently been demonstrated above 10 K. We discuss the extension of the entire digital readout to operating temperatures above 10 K.

Counting SFQ analog to digital converter results

We have characterized Nb analog to digital converters using a resistor-coupled SFQ flip flop counter and a latching destructive readout (DRO). The counter used SFQ buffers between bits to provide isolation during destructive readout. We have measured parallel readout at sample rates up to 125 MSPS. We have also successfully operated an ADC which has Josephson junction regulated flip flop gate and readout bias busses. Using a self-resetting gate (SRG) at the carry out of the counter, we have measured the bit error rates (BER) of the counters. A two junction SQUID quantizer, biased in the voltage state, was used to produce correlated SFQ pulses at each junction. The SRG outputs of two 10 bit counters connected to the two quantizer outputs were compared. We measured a BER of /spl sim/5/spl times/10/sup -11/ with the quantizer operating at 19 GHz. We believe the principle error source is the latching SRG.

Potential architectures for superconductive IR focal plane sensors

Extremely low power superconductive electronics (SCE) (low noise preamplifier, analog to digital converter, multiplexer, etc.) for very large focal plane arrays can significantly reduce the overall sensor system power, hence its weight and volume, thus reducing overall mission cost. The general architecture for a Z-plane, all-superconducting technology focal plane signal processor is presented illustrating the functional elements and their general configurations. The low noise and speed of the TRW developed SCE permits unique solutions to focal plane array signal processing issues such as in-line gamma suppression and digital signal integration.