John W. Spargo

Flux-1 RSFQ microprocessor: physical design and test results

The Flux-1 chip is an RSFQ implementation of a small general-purpose processing engine with target clock frequency of 20 GHz and over 5000 gates (over 60 K Josephson junctions) connected in an irregular pattern. The scale of this design task forced us to re-think conventional RSFQ design methodology and implement new approaches suitable for digital systems of this level of complexity and beyond. This paper presents lessons learned from the Flux-1 effort, mostly concentrating on chip physical design. Here we discuss our approach to the circuit design and verification of individual gates, gate interconnect using passive transmission lines and use of CAD tools for design automation and verification.

High data rate switch with amplifier chip

A critical component for high bandwidth communications links is a digital switch. Desirable features of a digital switch include: high input/output bandwidth, high channel count, scalability, low latency and interchannel skew. Superconductive circuits, with simultaneous high speed and low power advantages (even including the requisite cryocooler) have been applied to a highly scaleable crossbar switch, useful in supercomputer networks, massively parallel processing (MPP), and high data rate telecommunications. We report here on the testing of a 16/spl times/16 switch chip based on the switch chip component of the highly scaleable crossbar system. We have successfully transmitted multi-Gb/s data through this superconducting switch, with packet destination addressing decoded from the header of the data packet. The data are transmitted to a separate superconducting amplifier chip, mounted on a superconducting multi-chip module with the switch. The switch is a crossbar architecture, voltage state design, and operated to beyond 3 Gb/s. The amplifier is a clocked latching stack of Josephson junctions. Output of the amplifier at 6.2 Gb/s is 7.0 mV, which facilitates the interface of the module to its users. BER of the two-chip assembly is 10/sup -9/ or less above 2 Gb/s.

Single flux quantum crossbar switch

A crossbar switch has been designed using Single Flux Quantum (SFQ) gates exclusively for all internal functions. A 4/spl times/4 prototype has been fabricated in our Nb process foundry with J/sub c/ of 2000 A/cm/sup 2/. We report on the design and performance of the switch and of an individual crosspoint element at high data rates (/spl ges/1 Gbps). A novel design of a double-edge-triggered dc/SFQ converter is discussed. The requirements for output amplification and on-chip versus off-chip amplifier issues will be presented.

Design of a 10 K NbN A/D converter for IR focal plane array sensors

We are implementing a 12 bit SFQ counting ADC with parallel-to-serial readout using our established 10 K NbN capability. This circuit provides a key element of the analog signal processor (ASP) used in large infrared focal plane arrays. The circuit processes the signal data stream from a Si:As BIB detector array. A 10 mega samples per second (MSPS) pixel data stream flows from the chip at a 120 megabit bit rate in a format that is compatible with other superconductive time dependent processor (TDP) circuits being developed. We will discuss our planned ASP demonstration, the circuit design, and test results.<<ETX>>

Multi-Gb/s operation of flipped chip MVTL circuits

Development of a reliable flipped chip mounting technique enables demonstration of high speed, complex digital circuits. Flip chip mounting has greatly reduced parasitic inductance compared to conventional wire bonding, and permits remounting of known good die onto multi-chip modules. Superconductive digital circuits have operated to 4.3 Gb/s in our custom test station. The circuit and carrier are fabricated using TRWs foundry process. The chips are flipped onto a superconducting coplanar carrier using a low temperature solder reflow process reported on at this conference. Testing is performed in a multi-GHz, flip contact, variable temperature probe. This test facility is capable of testing circuits to 12 Gb/s. We will describe the operation and performance of our circuits at high bit rates, and design improvements intended to facilitate operation at higher bit rates with improved yield. In addition, we will discuss the use of a logic simulation tool to analyze the output words, and pinpoint the gate or gates that failed to operate properly.

Vision for single flux quantum very large scale integrated technology

Single flux quantum (SFQ) electronics is extremely fast and has very low on-chip power dissipation. SFQ VLSI is an excellent candidate for high-performance computing and other applications requiring extremely high-speed signal processing. Despite this, SFQ technology has generally not been accepted for system implementation. We argue that this is due, at least in part, to the use of outdated tools to produce SFQ circuits and chips. Assuming the use of tools equivalent to those employed in the semiconductor industry, we estimate the density of Josephson junctions, circuit speed, and power dissipation that could be achieved with SFQ technology. Today, CMOS lithography is at 90?65?nm with about 20 layers. Assuming equivalent technology, aggressively increasing the current density above 100?kA?cm?2 to achieve junction speeds approximately 1000?GHz, and reducing device footprints by converting device profiles from planar to vertical, one could expect to integrate about 250?M Josephson junctions cm?2 into SFQ digital circuits. This should enable circuit operation with clock frequencies above 200?GHz and place approximately 20?K gates within a radius of one clock period. As a result, complete microprocessors, including integrated memory registers, could be fabricated on a single chip.

Superconductive digital readout for IR FPA sensors

We have built and demonstrated an all superconductive digital readout for use in an IR focal plane array sensor. High performance, ultralow power superconductive circuits perform the functions of low noise preamplification and analog to digital conversion. The superconductive readout was tested with a variety of detectors, including InSb, Si:As, and a thin film NbN superconducting detector. Light sources included a HeNe laser (0.6 micron), a CO2 laser (10 microns), and a blackbody (400 to 900 K). In each case, the detector and readout circuitry was assembled into a 2 inch diameter, 6 inch long test package cooled in a single dewar. We demonstrated the functionality of the detector/readout channel from input photons to output digital signal. The superconductive readout reported here used Nb-based circuits operating at 4 K. An NbN squid amplifier and detector have subsequently been demonstrated above 10 K. We discuss the extension of the entire digital readout to operating temperatures above 10 K.

Optimization of NbN MVTL logic gates for 10 K operation

We have systematically studies designs for Modified Variable Threshold Logic Gates (MVTL) in NbN within the framework of factorial analysis. Our goal is to attain optimized margin and fanout for 10 K operation. Significant parasitic inductances, associated with current crowding at junction vias, were measured and are found to affect the operating margin. We report the progression of designs, margin measurements and yield data for our 10 K circuits.<<ETX>>

A three-terminal semiconductor-superconductor transimpedance amplifier

The authors report an improved hybrid three-terminal transimpedance amplifier (TIA) with significant current gain. The TIA consists of a semiconductor diode configured for injection of electrons into a thin base electrode (<25 nm) superconductor-insulator-superconductor junction, whose response is read out by low-impedance superconductive electronics. An input dynamic impedance greater than 10/sup 11/ Omega , an output dynamic impedance of approximately 10/sup -3/ Omega a current gain of 20, and an effective input noise current less than 10/sup -14/ A/ square root Hz were achieved. The TIA was operated in a sensor test bed with an extrinsic silicon infrared (IR) detector and superconductive analog-to-digital (A/D) converter. This device permits matching state-of-the-art semiconductor IR detectors with superconductive A/D converters, enabling a fully digital cryogenic focal plane array sensor with high sensitivity and speed but reduced power consumption.<<ETX>>

Digital Concepts and Applications

Superconductors have unique attributes that bring important benefits to digital components. Millivolt logic produces ultralow power gates, which operate at pico second delays. These ultralow-power gates reduce chip area power density. “Zero resistance” buses reduce voltage drops and cryogenic power supply waste. Very low surface resistance at RF and microwave frequencies produces low-loss and low-dispersion transmission lines for rf signals and picosecond pulses. Low-impedance logic circuits and correspondingly low-impedance transmission lines permit closely spaced lines with negligible crosstalk. Cryogenic temperature operation virtually eliminates thermally activated degradation and failure mechanisms in thin-film circuits, and produces very low thermal noise that permits lower power logic operation. Finally, because of their very small active volume, Josephson junctions are insensitive to alpha particle upsets. Thus, performance and circuit densities that are simply unattainable with semiconductors are possible in superconductor electronics. The utility of superconductivity for digital applications is recognized by the use of the “cryotron” as a superconducting switching device. Cryotron switching is based on inducing a phase transition from the superconducting state to the normal state in a superconducting line by the application of a magnetic field. While circuits based on the cryotron are demonstrated, the nascent silicon-based integrated circuit overtook these devices and made them footnotes in the technology of digital applications.