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Robert D. Shur

VLSI Technology

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design automation conference | 1985

A Behavioral Modeling System for Cell Compilers

James C. Althoff; Robert D. Shur

In this paper we describe a new behavioral modeling facility that addresses the special demands imposed by a cell compiler-based design system. We present a flexible parameter mechanism that makes it possible to describe cells whose pin configurations vary according to user-supplied parameter values. We also introduce the PRICE timing model which provides for detailed timing descriptions.

Archive | 1993

Automated optimization of hierarchical netlists

Arnold Ginetti; Thomas J. Schaefer; Robert D. Shur; Christopher H. Kingsley

Archive | 1989

Event-controlled LCC stimulation

Thomas J. Schaefer; Robert D. Shur

Archive | 1990

System and method for setting capacitive constraints on synthesized logic circuits

Mark R. Hartoog; Thomas J. Schaefer; Robert D. Shur

Archive | 1991

System and method for synthesizing logic circuits with timing constraints

Thomas J. Schaefer; Robert D. Shur

Archive | 1989

Levelized logic simulator with fenced evaluation

Thomas J. Schaefer; Robert D. Shur

Archive | 1997

Enhanced dynamic programming method for technology mapping of combinational logic circuits

Thomas J. Schaefer; Robert D. Shur

Archive | 1990

Circuit simulation system with wake-up latency

Steve Bush; Robert D. Shur

Archive | 1992

Buffer circuit design using back track searching of site trees

Thomas J. Schaefer; Robert D. Shur

Archive | 1990

INTEGRATED PARITY-BASED TESTING FOR INTEGRATED CIRCUITS

Mark R. Hartoog; James A. Rowson; Robert D. Shur; Kenneth D. Van Egmond

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Thomas J. Schaefer

VLSI Technology

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Mark R. Hartoog

VLSI Technology

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Arnold Ginetti

VLSI Technology

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Christopher H. Kingsley

VLSI Technology

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James A. Rowson

VLSI Technology

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James C. Althoff

VLSI Technology

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Kenneth D. Van Egmond

VLSI Technology

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Steve Bush

VLSI Technology

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