Robert Fuller

Reduction of CMP /spl mu/-scratch induced metal shorts by introduction of a post CMP tungsten plasma clean process in a high volume DRAM manufacturing environment

A common problem of tungsten CMP processes used in damascene sequences is the generation of /spl mu/-scratches. These scratches form small trenches in the oxide, which are filled with tungsten during the CMP process. These metal filled trenches can short the intended patterned circuitry. By introduction of a dry plasma clean after the tungsten CMP process, the yield impact of these scratches can be reduced or eliminated: The plasma etch process removes tungsten uniformly both from the intended metal pattern and the unintended metal residue in the scratch trench. The metal short can be eliminated by adjusting the etch depth to the actual scratch depth.

Deep Trench Resistance and leakage Reduction -- Poly1 Doping Process Optimization in High Volume DRAM Manufacturing for 300mm Factory

In this paper, we describe the influence of arsenic doped poly-silicon on signal margin and node leakage current of 110 nm deep trench DRAM products. Methods on optimizing both physical and electrical qualities of poly-silicon are presented and challenges of quick electrical characterization of the new process for rapid yield learning are discussed. Finally, how these methods can be applied to other poly layers and to the next generation devices are briefly discussed