Robert Harold Krambeck

Implanted‐Barrier Two‐Phase Charge‐Coupled Device

A new kind of charge‐coupled device (CCD) utilizing an ion‐implanted barrier and only two nonoverlapping electrodes per bit is described. The use of implanted charge substantially simplifies device structure. The two‐electrode‐per‐bit configuration permits operation with only one clock. In addition, the device performs better than any previously reported CCD with a loss per transfer of less than 0. 1% up to 6. 5 MHz and 2% at 17 MHz.

Conductively connected charge-coupled device

A new kind of charge-coupled device, the conductively connected charge-coupled device (C4D) has been built and operated. This device is formed by providing self-aligned, source-drain diffusions (or implants) between adjacent, refractory electrodes of a two-phase, ion implanted-barrier CCD. These implants eliminate the inherently unstable exposed channel region presently found in CCDs with coplanar gates, without resorting to overlapping gates. Shift registers ranging from 16 to 128 b in length were evaluated and in spite of low mobilities (80 cm2/V.s) and low barrier heights (2-3 V), incomplete transfer losses of 0.2 percent per transfer were measured at 1 MHz clock frequency. Fabrication has been demonstrated to be quite compatible with p-channel refractory gate IGFET technology, and because the sensitive interelectrode region of the C4D is heavily doped, these devices should show the same reliability as conventional circuits made with the same technology.

Implanted barrier two phase CCD

Any charge coupled device must have a surface potential pattern in each bit such that charge always transfers in the same direction. In the two phase device to be described, the mobile charge is forced forward by a strip of repulsive fixed charge at the input end of each electrode. This strip of charge can be obtained quite conveniently and reproducibly by means of ion implantation. It will be shown that the implant permits substantial simplification of the metallization pattern compared with other CCDs and as a result, the device is easier to fabricate and high yields are easy to obtain.

A conductively connected charge coupled device

From the viewpoint of the fabricator and user, a charge coupled device should be two-phase, have no requirement for narrow metal gaps, use only a single type of insulated gate structure, require little change in standard IGFET processing, and offer the same reliability that other circuits have. The Conductively Connected Charge Coupled Device (C4D) satisfies these requests.

Low frequency transfer efficiency of E-beam fabricated conductively connected charge-coupled device

Theoretical calculations are made of low frequency transfer inefficiency for the conductively connected charge-coupled device (C4D). Two mechanisms for transfer inefficiency arise in the C4D which are not found in correctly operated charge-coupled devices (CCDs) but are found in bucket brigade devices. These are 1) barrier length modulation and 2) diffusion over the barrier. Theoretical analyses are made for both of these mechanisms, and both are found to be significant (∼0.05 percent/transfer for a 5/µm barrier) and independent of frequency. The transfer inefficiency increases sharply as feature size is reduced but decreases as oxide thickness is reduced. The fabrication and testing of C4Ds with barrier lengths in the range 1.75 µm to 5 µm are described, and the measured transfer inefficiencies compare well with theoretical predictions.

Transfer efficiency of e-beam fabricated C4D'S

In this work a quantitative analysis of the low frequency loss mechanisms of presented. It will be shown that the loss is caused by changes in the shape and height of the implanted potential carrier. The loss is approximately inversely proportional to feature size and directly proportional to oxide thickness. Experimental data on electron beam fabricated devices will be given that shows good agreement with the theoretical calculations. It will be shown that for a 500 A oxide, usable devices were made with areas as small as 125 µ2 (.2mil2) per bit.