Robert J. Francis

Chortle-crf: Fast technology mapping for lookup table-based FPGAs

A new technology mapping algorithm for lookup tablebased Field Programmable Gate Arrays (FPGA) is presented. The major innovation is a method for choosing gate-level decompositions based on bin packing. This approach is up to 28 times faster than a previous exhaustive approach. The algorithm also exploits reconvergent paths and replication of logic at fanout nodes to reduce the number of lookup tables in the circuit. The new algorithm is implemented in the Chortle-crf program. In an experimental comparison Chortle-crf requires 14 YO fewer lookup tables than Chortle [Fran90] and 10 ~o fewer lookup tables than mis-pga [Murg90a] to implement a set of benchmark networks. Chortle-crf can also implement a network as a circuit of Xilinx 3000 series Configurable Logic Blocks (CLBS). To implement the benchmark networks as circuits of CLBS Chortle-crf requires 12 70 fewer CLBS than mis-pga and 22 % fewer CLBS than XNFOPT [Xili89]. In these experiments Chortle-crf waa an average of 68 times faster than mis-pga and 30 times faster than XNFOPT. 1

Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency

The relationship between the functionality of a field-programmable gate array (FPGA) logic block and the area required to implement digital circuits using that logic block is examined. The investigation is done experimentally by implementing a set of industrial circuits as FPGAs using CAD (computer-aided design) tools for technology mapping, placement, and routing. A range of programming technologies (the method of FPGA customization) is explored using a simple model of the interconnection and logic block area. The experiments are based on logic blocks that use lookup tables for implementing combinational logic. Results indicate that the best number of inputs to use (a measure of the blocks functionality) is between three and four, and that a D flip-flop should be included in the logic block. The results are largely independent of the programming technology. More generally, it was observed that the area efficiency of a logic block depends not only on its functionality but also on the average number of pins connected per logic block. >

Chortle: a technology mapping program for lookup table-based field programmable gate arrays

Field Programmable Gate Arrays are new devices that combine the versatility of a Gate Array with the user-programmability of a PAL. This paper describes an algorithm for technology mapping of combinational logic into Field Programmable Gate Arrays that use lookup table memories to realize combinational functions. It is difficult to map into lookup tables using previous techniques because a single lookup table can perform a large number of logic functions, and prior approaches require each function to be instantiated separately in a library. The new algorithm, implemented in a program called Chortle uses the fact that a K-input lookup table can implement any Boolean function of K-inputs, and so does not require a library-based approach. Chortle takes advantage of this complete functionality to evaluate all possible decompositions of the input Boolean network nodes. It can determine the optimal (in area) mapping for fanout-free trees of combinational logic. In comparisons with the MIS II technology mapper, on MCNC-89 Logic Synthesis benchmarks Chortle achieves superior results in significantly less time. 1

Technology mapping of lookup table-based FPGAs for performance

A novel technology mapping algorithm that reduces the delay of combinational circuits implemented with lookup-table-based field-programmable gate arrays (FPGAs) is presented. The algorithm reduces the contribution of logic block delays to the critical path delay by reducing the number of lookup tables on the critical path. The key feature of the algorithm is the use of bin packing to determine the gate-level decomposition of every node in the network. In addition, reconvergent paths and the replication of logic at fanout nodes are exploited to further reduce the depth of the lookup table circuit. For fanout-free trees the algorithm will construct the optimal depth K-input table circuit when K is less than or equal to 6.<<ETX>>

The effect of logic block complexity on area of programmable gate arrays

The authors explore the tradeoff between the area of a programmable gate array (PGA) and the functionality of its logic block. A set of industrial circuits is implemented as PGAs using tools for technology mapping, placement, and routing. A simple model allows the exploration of a range of programming technologies and accounts for the area required by wiring. Experiments indicate that for combinational logic blocks implemented using lookup tables, the best number of inputs to use is between three and four, and that a D flip-flop should always be included in the logic block. These results are independent of the programming technology

Ganged CMOS: trading standby power for speed

The authors present ganged-CMOS logic (GCMOS), a technique employing CMOS inverters with their outputs shorted together, driving one or more encoding inverters. These encoding inverters, serving to quantize the nonbinary signal at the ganged node, effectively buffer it from external circuitry, thus allowing locally smaller noise margins. As demonstrated by two novel adders, GCMOS achieves higher speeds and lower input capacitances than static CMOS, at the expense of higher static power dissipation. Monte Carlo simulations have shown that extremely tight process control is not needed to ensure correct operation; however, it is required to obtain optimum circuit performance. >

A tutorial on logic synthesis for lookup-table based FPGAs

Discusses combinational logic synthesis for FPGAs that use lookup tables (LUTs). Issues that differentiate LUT synthesis from conventional logic synthesis are emphasized. The ability of a K-input LUT to implement any Boolean function of K variables differentiates the synthesis of LUT circuits from that for conventional ASIC technologies. The major different occurs during the technology mapping phase of logic synthesis. For values of K greater than 3, the larger number of functions that can be implemented by a K-input LUT makes it impractical to use a conventional library-based technology mapping. However, the completeness of the set of functions that can be implemented by a LUT eliminates the need for a library of separate functions. In addition, this completeness can be leveraged to optimize the final circuit.<<ETX>>

Swamp: a fast processor for Smalltalk-80

A processor for the Smalltalk-80↑ programming language is described. This machine is implemented using a standard bit slice ALU and sequencer, TTL MSI, and NMOS LSI RAMS. It executes an instruction set similar to the Smalltalk-80 virtual machine instruction set. The data paths of the machine are optimized for rapid Smalltalk-80 execution by the inclusion of a context cache, tag checking, and a hardware method cache. Each context is only partly initialized when created, and has no memory allocated for it until a possibly non-LIFO reference to it is created. The machine is microprogrammed, and uses a simple next micro-address prediction strategy to obtain most of the performance of pipelining without the attendant complexity. The machine can execute simple instructions at over 7M bytecodes per second and has a predicted average throughput of 1.9M bytecodes per second. A processor for the Smalltalk-80↑ programming language is described. This machine is implemented using a standard bit slice ALU and sequencer, TTL MSI, and NMOS LSI RAMS. It executes an instruction set similar to the Smalltalk-80 virtual machine instruction set. The data paths of the machine are optimized for rapid Smalltalk-80 execution by the inclusion of a context cache, tag checking, and a hardware method cache. Each context is only partly initialized when created, and has no memory allocated for it until a possibly non-LIFO reference to it is created. The machine is microprogrammed, and uses a simple next micro-address prediction strategy to obtain most of the performance of pipelining without the attendant complexity. The machine can execute simple instructions at over 7M bytecodes per second and has a predicted average throughput of 1.9M bytecodes per second.

Routing for FPGAs

In Chapter 3, technology mapping in CAD systems for FPGAs was discussed in detail. The next step in such systems is the placement of the logic blocks. This problem in the FPGA environment is very similar to placement tasks for other technologies, for example standard cells. A number of efficient techniques for placement have already been developed and well documented in the technical literature [Hana72] [Sech87]. Since these techniques can easily be adapted to use for FPGAs, we will not pursue the placement task in this book. This chapter focuses on the next step in the CAD system, where the routing of interconnections among the logic blocks is realized. As Figure 5.1 indicates, routing is the final phase of a circuit’s implementation, after which the FPGA can be configured by a programming unit.

Introduction to FPGAs

Very Large Scale Integration (VLSI) technology has opened the door to the implementation of powerful digital circuits at low cost. It has become possible to build chips with more than a million transistors, as exemplified by state-of-the-art microprocessors. Such chips are realized using the full-custom approach, where all parts of a VLSI circuit are carefully tailored to meet a set of specific requirements. Semi-custom approaches such as Standard Cells and Mask-Programmed Gate Arrays (MPGAs) have provided an easier way of designing and manufacturing Application-Specific Integrated Circuits (ASICs).