Robert L. Schmid

On the Analysis and Design of Low-Loss Single-Pole Double-Throw W-Band Switches Utilizing Saturated SiGe HBTs

This paper describes the analysis and design of saturated silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) switches for millimeter-wave applications. A switch optimization procedure is developed based on detailed theoretical analysis and is then used to design multiple switch variants. The switches utilize IBMs 90-nm 9HP technology, which features SiGe HBTs with peak f T/ fmax of 300/350 GHz. Using a reverse-saturated configuration, a single-pole double-throw switch with a measured insertion loss of 1.05 dB and isolation of 22 dB is achieved at 94 GHz after de-embedding pad losses. The switch draws 5.2 mA from a 1.1-V supply, limiting power consumption to less than 6 mW. The switching speed is analyzed and the simulated turn-on and turn-off times are found to be less than 200 ps. A technique is also introduced to significantly increase the power-handling capabilities of saturated SiGe switches up to an input-referred 1-dB compression point of 22 dBm. Finally, the impact of RF stress on this novel configuration is investigated and initial measurements over a 48-h period show little performance degradation. These results demonstrate that SiGe-based switches may provide significant benefits to millimeter-wave systems.

Total Dose and Transient Response of SiGe HBTs from a New 4th-Generation, 90 nm SiGe BiCMOS Technology

The total ionizing dose and laser-induced transient response of a new 4th generation 90 nm IBM SiGe 9HP technology are investigated. Total dose testing was performed with 63.3 MeV protons at the Crocker Nuclear Laboratory at the University of California, Davis. Transient testing was performed on the two-photon absorption system at Naval Research Laboratory. Results show that the SiGe HBTs are dose-tolerant up to 3 Mrad(SiO2) and exhibit reduced single event transients compared to earlier SiGe generations.

A Low-Loss and High Isolation D-Band SPDT Switch Utilizing Deep-Saturated SiGe HBTs

A single-pole double-throw switch, utilizing double-shunt, deep-saturated HBTs is implemented in a 0.13 μm SiGe BiCMOS technology, occupying 0.36 mm2 of IC area. A superior switch performance is identified when HBTs are operated in saturation regime, and state of the art performance is achieved at D-band frequencies from 96 to 163 GHz. Measurements show a minimum insertion loss of 2.6 dB at 120 and 150 GHz, a highest isolation of 29 dB at 120 GHz and an input 1 dB compression point of 17 dBm at 94 GHz, outperforming similar implementations in deep-scaled CMOS technologies.

A 94 GHz, 1.4 dB Insertion Loss Single-Pole Double-Throw Switch Using Reverse-Saturated SiGe HBTs

This work demonstrates two 94 GHz SPDT quarter-wave shunt switches using saturated SiGe HBTs. A new mode of operation, called reverse saturation, using the emitter at the RF output node of the switch, is utilized to take advantage of the higher emitter doping and improved isolation from the substrate. The switches were designed in a 180 nm SiGe BiCMOS technology featuring 90 nm SiGe HBTs (selective emitter shrink) with fT/fmax of 250/300+ GHz. The forward-saturated switch achieves an insertion loss and isolation at 94 GHz of 1.8 dB and 19.3 dB, respectively. The reverse-saturated switch achieves a similar isolation, but reduces the insertion loss to 1.4 dB. This result represents a 30% improvement in insertion loss in comparison to the best CMOS SPDT at 94 GHz.

Analysis and design of a 3–26 GHz low-noise amplifier in SiGe HBT technology

The analysis and design of a wideband silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) low noise amplifier (LNA) is presented. Resistive shunt-shunt feedback is employed to achieve wideband gain and matching characteristics and it is shown that the addition of small reactive elements can extend the bandwidth of the amplifier significantly. Measured data for the LNA, implemented in a 130-nm SiGe BiCMOS technology, show 9 dB gain with less than 1.0 dB variation across 3-26 GHz, and input and output return losses better than -10 dB over the entire bandwidth. The measured noise figure (NF) is less than 5 dB from 3-18 GHz and rises to only 6.5 dB at 24 GHz. In addition, the amplifier exhibits excellent linearity performance, with a input-referred third-order intercept point (IIP3) of 5.8 dBm and input-referred 1 dB compression point (P1dB) of -5.6 dBm. This SiGe amplifier occupies 0.48 mm2 (including pads) and consumes 33 mW of power while operating off a 3.3 V supply.

Best practices to ensure the stability of sige HBT cascode low noise amplifiers

This work provides a detailed examination of the stability of SiGe cascode low noise amplifiers (LNAs). The upper base is identified as a problematic node for stability. S-probe simulations are used to extract reflection coefficients internal to the circuit and provide insight on how to improve the stability of a cascode amplifier and thereby establish “best practices” for designers. These techniques are incorporated into a cascode LNA design fabricated on a 180 nm, 150 GHz fT SiGe BiCMOS technology. The measured SiGe LNA has a gain of 16.5 dB and a noise figure of 2.1 dB at a center frequency of 9.2 GHz. A series of measurements using tuners at both the input and output confirm the LNA is stable for all impedances covered by the tuners (|Γ| <; 0.8).

A Comparison of the Degradation in RF Performance Due to Device Interconnects in Advanced SiGe HBT and CMOS Technologies

This paper investigates the impact of the interconnect between the bottom and the top metal layers on the transistor RF performance of CMOS and silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technologies. State-of-the-art 32-nm silicon-on-insulator (SOI) CMOS and 120-nm SiGe HBT technologies are analyzed in detail. Measured results indicate a significant reduction in the unity-gain frequency (fT) from the bottom to the top metal layer for advanced CMOS technology nodes, but only a slight reduction for SiGe HBTs. The 32-nm SOI CMOS and SiGe HBT technologies have a reduction in the maximum oscillation frequency (fmax) from the bottom to the top metal layer of ~12% and 5%, respectively. By analyzing technology scaling trends, it is clear that SiGe HBTs can now achieve a similar peak fT at the top metal layer in comparison with advanced CMOS technology nodes, and a significantly higher fmax. Furthermore, in CMOS technologies, the top metal layer fmax appears to have reached a peak around the 45-65-nm technology nodes, a result which has significant implications.

A D-band (110 to 170 GHz) SPDT switch in 32 nm CMOS SOI

This work demonstrates the implementation of a D-band single-pole double-throw switch(SPDT) in 32 nm CMOS SOI technology. A tuned shunt topology is used to achieve the lowest insertion loss. The switch demonstrates state-of-the art performance showing an insertion loss of 2.6 dB at 140 GHz and good matching across the whole D-band. Measurements also show high isolation of greater than 20 dB from 110 to 170 GHz. This is the lowest insertion loss of an SPDT switch that has been designed for the D-band and reported in a 32 nm CMOS SOI process.

A compact, transformer-based 60 GHz SPDT RF switch utilizing diode-connected SiGe HBTs

This work describes the design of a compact 60 GHz SPDT RF switch utilizing diode-connected SiGe HBTs. At mm-wave frequencies, SiGe HBTs demonstrate better Roff/Ron ratios than CMOS and can be used to improve switch performance. A switch topology using a transformer is developed to create a SPDT with a small foot print of 190 μm × 225 μm. The transformer design is discussed and a methodology is presented to optimize the matching components of the switch. The switch is fabricated on a 180 nm SiGe BiCMOS technology platform featuring HBTs with an fT/fmax of 240/260 GHz. The switch achieves 2.7 dB insertion loss and 14 dB isolation at 60 GHz with a P1dB and IIP3 of 13.8 dBm and 23.8 dBm, respectively. This represents a 20% improvement in insertion loss in comparison to a similar 90 nm CMOS switch at 50 GHz. It is also shown that the proposed switch can help enable built-in-self-test (BIST) functionality for transmit-receive modules.

Characterization of a low-loss and wide-band (DC to 170 GHz) flip-chip interconnect on an organic substrate

This paper, for the first time, presents the characterization of a very wide-band flip-chip interconnect from DC to 170 GHz on a liquid crystal polymer substrate. The performance is optimized by modeling the structure in a 3-D electromagnetic simulation software. To mitigate the influence of the capacitive effect caused by the flip-chip overlap section, high impedance inductive sections are used. The measured return loss is more than 10 dB, while the insertion loss is less than 0.9 dB/mm for the transmission line and the interconnect across the entire frequency range. The measurements correlate well with simulated results.