Robert L. Vyne

A 1 V BiCMOS rail-to-rail amplifier with n-channel depletion-mode input-stage

This amplifier is fabricated on a SMARTMOS/sup TM/ flow with depletion-mode nMOS, vertical p-n-p, and high-frequency n-p-n transistors. Most techniques for achieving rail-to-rail input stage performance concentrate on the use of complementary bipolar or enhancement MOSFET devices to allow the amplifier common-mode range to include both supply rails. These techniques require a minimum supply voltage of 1.8 V for bipolar and 3 V for CMOS to allow a transition from sensing common mode voltages at ground when the p-n-p or pMOS pair is active, to sensing common-mode voltages at the positive supply when the n-p-n or nMOS pair is active. This amplifier uses a single pair of depletion-mode nMOS devices to allow low-voltage, rail-to-rail operation.

A monolithic p-channel JFET quad op amp with in-package trim and enhanced gain-bandwidth product

An amplifier that uses an analog resistive trim element (trimistor) that can be reduced in value by Al/Si filaments formed by an alloying process is described. Filament generation and their lengths are controlled by current pulses through the element. A general in-package trim technique was developed using the trimistor and a high-voltage high-current diode, allowing the package pins to be multifunctional. This combination permits the input offset voltage for each channel of a quad op amp to be trimmed in the package to 10 /spl mu/V. The differential input stage utilizes JFET followers, which allows the separation of JFET/bipolar biasing currents. This results in a low offset voltage temperature coefficient (1/spl sigma/) of 2.5 /spl mu/V//spl deg/C. The gain-bandwidth product is enhanced over the unity-gain frequency by using a dual-doublet frequency-compensation technique. One doublet is defined using the JFET follower with feedforward capacitance, and the second doublet is formed by local positive AC feedback applied to the input current mirror. The amplifier is unity-gain stable, with a 100 MHz gain-bandwidth product (at 100 kHz) and 25 V//spl mu/S slew rate. The symmetrical quad layout is 80/spl times/120 mil/SUP 2/ with 6% of the area dedicated to trim. The die is suitable for a 14-pin narrow-body surface-mount package.

Design techniques for improving the HF response of a monolithic JFET operational amplifier

Bandwidth limitations of an operational amplifier are explored in relation to the second-order frequency response caused by the output followers inductive emitter impedance when driving capacitive loads or by the local AC feedback associated with the Miller integration function. The substrate p-n-p follower is shown to seriously degrade the bandwidth in the sink mode due to its low /spl omega//SUB /spl tau//. New design techniques are discussed which use the integration capacitor to provide local AC feedback around a new all-n-p-n transistor output stage. This reduces both the open-loop distortion and the quiescent output resistance for a given quiescent current. This also maximizes the lower limit of the inductive frequency range in the sink mode to improve the second-order frequency responses when driving capacitive loads. The multipole local AC feedback loop (Miller loop) is analyzed, and a method of compensation is described which uses pole splitting and feedforward techniques within the Miller loop. As a result, a general-purpose monolithic p-channel JFET quad operational amplifier has been fabricated with standard low-cost technology; the amplifier achieves a 10-MHz bandwidth and a 45-V//spl mu/s slew rate, while consuming only 2.1 mA/amplifier.

A quad low voltage rail-to-rail operational amplifier

A low-voltage rail-to-rail amplifier that has a NPN PNP switchable differential input stage allowing rail-to-rail input voltage swings is presented. The inputs can be overdriven without causing phase reversal in the output signal. The amplifier provides rail-to-rail output voltage swings which extend to within 50 mV of either rail. The output stage is current boosted to provide up to 50 mA of drive current.<<ETX>>

Sleep-mode amplifier

A novel technique for designing micropower operational amplifiers is described. An amplifier that operates in two separate states-sleep-mode and awake mode-is presented. Although the amplifier draws only 40 mu A of drain current while operating in the sleep-mode, it is able to drive 50 mA of output current when it transitions to the awake-mode. Transition between the two states is automatic, depending on the output current driving requirement.<<ETX>>

A trimmable P-channel JFET quad opamp

A 10μV offset opamp obtained by analog trimming will be reported. The circuit has a 100MHz gain-bandwidth product and a 25V/μs slew rate, using feedforward and local positive feedback. Die size is 80×120mils, and input offset current is 6pA.