William F. Davis
Motorola
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Featured researches published by William F. Davis.
IEEE Journal of Solid-state Circuits | 1987
Robert L. Vyne; William F. Davis; D.M. Susak
An amplifier that uses an analog resistive trim element (trimistor) that can be reduced in value by Al/Si filaments formed by an alloying process is described. Filament generation and their lengths are controlled by current pulses through the element. A general in-package trim technique was developed using the trimistor and a high-voltage high-current diode, allowing the package pins to be multifunctional. This combination permits the input offset voltage for each channel of a quad op amp to be trimmed in the package to 10 /spl mu/V. The differential input stage utilizes JFET followers, which allows the separation of JFET/bipolar biasing currents. This results in a low offset voltage temperature coefficient (1/spl sigma/) of 2.5 /spl mu/V//spl deg/C. The gain-bandwidth product is enhanced over the unity-gain frequency by using a dual-doublet frequency-compensation technique. One doublet is defined using the JFET follower with feedforward capacitance, and the second doublet is formed by local positive AC feedback applied to the input current mirror. The amplifier is unity-gain stable, with a 100 MHz gain-bandwidth product (at 100 kHz) and 25 V//spl mu/S slew rate. The symmetrical quad layout is 80/spl times/120 mil/SUP 2/ with 6% of the area dedicated to trim. The die is suitable for a 14-pin narrow-body surface-mount package.
IEEE Journal of Solid-state Circuits | 1984
William F. Davis; Robert L. Vyne
Bandwidth limitations of an operational amplifier are explored in relation to the second-order frequency response caused by the output followers inductive emitter impedance when driving capacitive loads or by the local AC feedback associated with the Miller integration function. The substrate p-n-p follower is shown to seriously degrade the bandwidth in the sink mode due to its low /spl omega//SUB /spl tau//. New design techniques are discussed which use the integration capacitor to provide local AC feedback around a new all-n-p-n transistor output stage. This reduces both the open-loop distortion and the quiescent output resistance for a given quiescent current. This also maximizes the lower limit of the inductive frequency range in the sink mode to improve the second-order frequency responses when driving capacitive loads. The multipole local AC feedback loop (Miller loop) is analyzed, and a method of compensation is described which uses pole splitting and feedforward techniques within the Miller loop. As a result, a general-purpose monolithic p-channel JFET quad operational amplifier has been fabricated with standard low-cost technology; the amplifier achieves a 10-MHz bandwidth and a 45-V//spl mu/s slew rate, while consuming only 2.1 mA/amplifier.
international solid-state circuits conference | 1972
William F. Davis; T.M. Frederiksen
A high-performance low-cost IC time-delay generator has been developed to be used as a building block for automotive electronic fuel injection systems. Time-delay accuracies are achieved by employing the IC to precisely control both the reset time and the initial ramp voltage of an external RC voltage sweep circuit by means of a gated voltage regulator. Reference information, derived from the rotating distributor shaft, triggers an input flip-flop that controls a reset generator to produce the required gating pulses. The resulting exponential voltage sweep is sensed at the input of three externally programmable voltage comparators that provide three separate time-delayed output signals within a /spl plusmn/1-percent accuracy from -40/spl deg/ to +125/spl deg/C. This technique is contrasted to a linear voltage sweep approach which offers less desensitivity to IC parameter variations.
international solid-state circuits conference | 1984
William F. Davis; R. Vyne
A 10MHz amplifier with a 45V/μs slew rate, and 1.8μs settling time to 1/2LSB of 12b (10V step), will be covered. An NPN output stage and compensated Miller amplifier provides 500pF drive, 55° phase and 5dB gain margins over (+14/-14.7) V output swing.
international solid-state circuits conference | 1987
Robert L. Vyne; William F. Davis; D. Susak
A 10μV offset opamp obtained by analog trimming will be reported. The circuit has a 100MHz gain-bandwidth product and a 25V/μs slew rate, using feedforward and local positive feedback. Die size is 80×120mils, and input offset current is 6pA.
international solid-state circuits conference | 1975
William F. Davis
The significant economic and performance advantages which may be realized over conventional monolithic techniques by employing, on a monolithic process, digital devices or compatible analog and digital devices to provide either analog and digital functions or improve analog circuit performance, will be assessed.
international solid-state circuits conference | 1973
William F. Davis
IC design techniques to protect the IC from destructive voltage transients and eliminate detrimental noise-induced substrate injection of electrons, using a minimum number of less expensive discrete components to produce a cost-effective automotive electronic system, will be discussed.
Archive | 1971
William F. Davis; Ronald W. Russell; Thomas M. Frederiksen; Ernest L. Long
Archive | 1982
William F. Davis
Archive | 1987
William F. Davis