Robert Newman

Optimizing assembly factors to minimize interlayer die stress in a PBGA package

As die have increased in complexity and density, there has been an associated growth in the number of die layers. To maximize field reliability interlayer die stress over use conditions should be minimized, which will minimize the occurrence of die layer delamination and associated die cracking failures. Interlayer die stress is affected by various packaging and assembly parameters, such as die thickness, die attach epoxy fillet geometry, molding compound, and saw cut process. Twenty-four lots of plastic ball-grid array (PBGA) packages were assembled in a 35/spl times/35 mm PBGA-352, as separate legs of a design of experiments (DOE). The die thickness was varied between 6 and 14 mils, in increments of 2 mils. The die were attached with three different fillet height geometries; standard fillet height (50% all around with no mismatch), hi/low fillet height (90% on one side of the die and 25% fillet height on the side opposite), and hi/even fillet height (90% all around with no mismatch). Each lot was subjected to reliability testing to determine which combination of assembly parameters yielded the most robust PBGA package. A PBGA package assembled with a 12 mil thick die and standard fillet produced the most robust product. The data indicates that the molding compound type and saw cut process did not affect the robustness of the package over the range of molding compounds and saw cut processes studied. The data also indicates that the thickness of the die is the parameter that most directly affects die cracking. In addition, the geometry of the fillet height also contributes to mechanical stress on the die, though the magnitude of its contribution is not as great. Two-dimensional mechanical modeling supports the experimental results. Furthermore, mechanical modeling provides a qualitative analysis of the stress induced on the die from the fillet geometry as well as the relationship between die thickness and package induced die stress.

Improvement on coined solder surface on organic substrate for flip chip attach yield improvement

This paper describes the improvement on coined solder surface of organic substrate to reduce flip chip assembly defects namely chip misalignment and contact non-wet. Roughening of the eutectic solder surface of the substrate helped to reduce bump misalignment for all packages especially for the tight bump pitch package. Additional pin reflow process for land grid array (LGA) substrates had proven to eliminate contact non wet issue. The surface morphology of the eutectic Sn/Pb bumps in the evaluations is characterized by Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM) and X-ray Photoelectron Spectroscopy (XPS). The condition of the solder joint is confirmed by chip pull test, x-ray and electrical test, using open/short test program.