Chu-Chung Lee

Challenges of Cu wire bonding on low-k/Cu wafers with BOA structures

This study describes the development of a Cu wire bond assembly solution for ICs using low dielectric constant (low K) dielectrics and Cu interconnect, with bond pads designed with aggressive BOA (Bond Over Active) design rules. The various wire bonding challenges imposed by the bond pad material stack and the aggressive high density BOA design will be discussed. It is desired to use the aggressive BOA rules since this provides greater design flexibility and can result in a smaller die size. The suitability of two different bond pad and BOA structures, currently used with Au wire bonding, was evaluated to assess viability for high reliability Cu wire bonding. The assembly process, the bond quality requirements, the reliability stress testing, and the impact on the Cu wire bonds will be described. Corrosion of the Cu-Al IMC (interface metallic compound) bond phase(s) that can be seen with environmental stress testing will be discussed. The hypothesis that the IMC corrosion is due to attack by impurities in the epoxy-based molding compound will be discussed. The results of a thermal aging study (150°C / 504 hrs), demonstrating the slow growth of the CuAl IMC structure, and analysis of the Cu-Al IMC phases will also be reported.

Overview of Metal Lifted Failure Modes During Fine-Pitch Wirebonding Low K/Copper Dies with Bond Over Active (BOA) Circuitry Design

The size of IC device has been reduced resulting from the reduction of both transistor gate length and bond pad pitch. Since 180 nm node, wafer fab technology has decreased the gate length more aggressively than the assembly site does with bond pad pitch. Both bond over active (BOA) and fine pitch wirebonding have been implemented simultaneously in order to minimize the white space area in the die. Combination of BOA, fine pitch wire bonding and low k/copper technology have thus become a new development scope for wire bonding technology development works. Several failure modes have been observed while utilizing this new technology combo. The Aluminum Cap Lift yield loss during the wirebond process was reported. The delaminated interface is Ta and copper at the aluminum cap bonding pad region. The Copper Metal Lift failure was also observed for FSG (fluorine-doped silicon glass) -Copper wafer technology. Copper Metal Lift failure is defined as the delaminated interface found between FSG and the barrier layer (e.g. Ta). The delamination interfaces for both Aluminum Cap Lift and Copper Metal Lift failures have been determined with several failure analysis techniques. Some of these techniques are standard FA tools such as TEM (Transmission Electron Microscope) and Auger depth profiling, and some are more special, e.g. nano-indentation. Root cause for each failure mode and its corresponding corrective actions will both be disclosed in this paper. Moreover, the Tilted Metal Lift failure was also observed during wire pull test as ball bond diameter reduced for fine pitch wirebonding. Its root cause will be disclosed too.

Copper wire bonding on low-k/copper wafers with Bond Over Active (BOA) structures for automotive customers

The gold price has continuously climbing since 2000 and is currently recorded at historical high at above USD1350 per ounce in October 2010 as compared to USD1000 per ounce one year ago. Gold wire bonding has been the primary wire interconnecting method used in the semiconductor packaging industry for more than 50 years. Gold wire historically represented about 20-25% of the package cost. With the ever increasing gold price, this ratio now can be as high as 30-35% of the package cost and does not look like there is a relief in sight. Replacing gold wire with copper wire has become a necessity in order to maintain low assembly cost for wire bonded parts. Copper wire has many benefits including low cost, high electrical and thermal conductivities and excellent reliability with aluminum pad metallization. Heavy gauge copper wire has been used in consumer products and semiconductor discrete products for a long time. Many commercial product sectors began thin gauge copper wire in production since 2008. Automotive customers are also forced to look for cheaper interconnecting alternative, such as copper wire as an example. One of the issues in qualifying copper wire for automotive customers with stringent reliability requirements is that no industrial standard has been agreed or published to define copper wire qualification requirements. Presently most companies still apply gold wire reliability requirement to qualify copper wire packages. Many of them extend the gold wire package reliability stress duration for copper wire as a safety factor during the qualification. Our study is aimed for the assembly solution to apply copper wires on low-k-copper wafers with aggressive Freescale Bond Over Active (BOA) rules to meet automotive qualification requirements of Automotive Electronics Council (AEC) grade 1 and grade 0. Two types of bonding surfaces were used in this study, namely the conventional aluminum bond pad and aluminum bond pad remetallized with Nickel / Palladium / Gold Over Pad Metallurgy (OPM). Since Cu-Al and Cu-Au systems are completely different from Au-Al system, the difficulty in applying the same Au wire standards to copper wire parts will be discussed. A new approach to defining the pass/ fail criteria for copper wire parts will be proposed in this study. Units assembled with fine gauge copper wire were submitted through extensive stress conditions in order to demonstrate the excellent package reliability performance.

Challenges in cavity-down thermally enhanced packages containing low-k die

The cavity-down thermally enhanced package such as Tape Ball Grid Array (TBGA) has the best thermal performance among the high pin count wire bonded package types because the silicon is attached directly onto a thick internal heat spreader. The TBGA package with low-k/Cu wafers has however challenged the assembly industry in passing package qualification requirement especially temperature cycling requirement. Low-k interlayer dielectric (ILD) material usually has the dielectric constant k of less than 3. The inherently weak adhesion in the low-k interconnect stack-up makes the silicon more susceptible to a failure mode called ILD crack or delamination that causes electrical failure during temperature related excursion such as temperature cycling test and board-level mounting. ILD delamination failure was reported not only at the die corner with highest stress concentration, but also on the die side away from the corner. Optical inspection of dicing quality at failing areas showed similar level of back-end-of-line (BEOL) peeling through scribe test structures that would have passed reliability testing when assembling in a conventional plastic ball grid array (PBGA). Mechanical analyses were performed to identify the specific failing interface within the stack of the back-end-of-line (BEOL) in the low-k die. 3D finite element model simulations were performed to analyze the stress distribution in the low-k die area. Structural parameters of the cavity-down TBGA package were modulated. The simulation analysis indicated that TBGA package applies a tensile stress on the top portion of the die edge region where the inter-layer dielectric (ILD) stacks are located when the package is subjected to temperature cycling tests. The tensile stress on the top portion of the die can be reduced by varying specific structural parameters of the TBGA package. A series of experiments was designed and conducted to validate the prediction of the mechanical simulation model. The simulation analysis supported by empirical data explained as to why the TBGA package is more susceptible to ILD delamination failures in temperature excursion condition in the presence of or lack of dicing defects. A special low stress glob top material was formulated and demonstrated a good production capability and package level reliability. The knowledge of the stress distribution in the TBGA system enabled the development of low stress glob top encapsulant that demonstrated a good production capability and package level reliability.

Challenges in Temperature Cycling Test for Electronic Packages Containing Low-K/Cu Silicon

The cavity-down thermally enhanced tape ball grid array (TBGA) package has generally challenged the assembly industry on passing package qualification requirement especially temperature cycling requirement when assembling low-k/Cu wafers. A mechanical stress simulation was conducted in order to assess the stress distribution in the low-k region of the silicon in the TBGA configuration. The simulation analysis indicated that the existing TBGA package applies a tensile stress on the top portion of die edge region where the inter-layer dielectric (ILD) stacks are located when the package is subjected to temperature cycling tests. A series of experiments was designed to validate the prediction of the mechanical simulation model. The knowledge of the stress distribution in the TBGA system enabled us to obtain an optimal solution for the combination of low-k dies and TBGA package to pass industrial-level qualification.