Robert Rogenmoser

Reducing Transistor Variability for High Performance Low Power Chips

CMOS integrated-circuit supply-voltage reduction has plateaued in recent years as increased transistor variability has limited transistor-threshold voltage scaling. The deeply depleted channel transistor, implemented on bulk CMOS, provides a low-cost option to re-enable voltage scaling on both future and legacy CMOS fabrication processes by reducing random variability and providing a strong body factor to pull in systematic variation and compensate for environmental effects resulting in 50 percent lower power at matched performance.

A 1 GHz power efficient single chip multiprocessor system for broadband networking applications

The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64/sup TM/ CPUs, a shared 512 KB L2 cache, a DDR memory controller, and integrated I/O. All major blocks of the processor are connected together via the ZBbus/sup TM/; a high speed split transaction fully coherent multi processor bus. Three Gigabit Ethernet MACs enable a direct interface to network elements. High-speed system I/O is provided using AMDs Lightning Data Transport (LDT/sup TM/) I/O fabric and a 66 MHz PCI bus. The die measures 14.2 mm by 13.3 mm in a bulk 0.15 /spl mu/m CMOS technology and has a power dissipation of 13 W at 1.2 V and 1 GHz.

A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions

A floating-point coprocessor, part of a MIPS64 dual-processor SOC, consists of a 32/spl times/64b register file and two pipes each with a multiplier, an adder, and a fast 3D approximation unit. It operates up to 1 GHz at 1.3 W, measures 4.74 mm/sup 2/ in 0.13 /spl mu/m CMOS, and has peak performance of 8 GFlops per CPU and 16 GFlops on the dual-processor SOC.

Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias

An SoC with ARM® Cortex™-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted Channel™ (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MHz speed via VDD scaling and body biasing. Alternatively DDC technology demonstrates 35% speed increase at matched power. The results hold across process corners and temperature with appropriate body bias selection. DDC technology also increases SRAM static noise margin (SNM) reduces 8Mb VDDmin by 150 mV reduces SRAM active leakage by 50% while maintaining Iread and reduces SRAM retention leakage by 5x.

A 2/spl times/ load/store pipe for a low-power 1-GHz embedded processor

The load/store pipe in an embedded processor is clocked at 2/spl times/ the processor clock frequency. It sustains two load or store operations per core clock cycle with zero load-to-use issue latency. The design is implemented in 0.13/spl mu/m 7M CMOS process and dissipates between 650 and 1090mW for core clock frequencies between 600MHz and 1GHz.

LVS verification across multiple power domains for a quad-core microprocessor

A unique LVS (layout-versus-schematic) methodology has been developed for the verification of a four-core microprocessor with multiple power domains using a triple-well 90-nm CMOS technology. The chip is migrated from its previous generation that is for a twin-well process. Due to the design reuse, VDD and GND are designed as global nets but they are not globally connected across the entire chip. The standard LVS flow is unable to handle the additional design complexity and there seems to be no published literature tackling the problem. This paper presents a two-phase LVS methodology: a standard LVS phase where power and ground nets are defined as global nets and a multi-power-domain LVS phase where power and ground nets are treated as local nets. The first phase involves verifying LVS at the block level as well as the full-chip level. The second phase aims at verifying the integrity of the multi-power-domain power grid that is not covered in the first phase LVS. The proposed LVS methodology was successfully verified by real silicon.