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Robert S. Chappell

Intel

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Featured researches published by Robert S. Chappell.

IEEE Micro | 2014

Haswell: The Fourth-Generation Intel Core Processor

Per Hammarlund; Alberto J. Martinez; Atiq Bajwa; David L. Hill; Erik G. Hallnor; Hong Jiang; Martin G. Dixon; Michael N. Derr; Mikal C. Hunsaker; Rajesh Kumar; Randy B. Osborne; Ravi Rajwar; Ronak Singhal; Reynold V. D'Sa; Robert S. Chappell; Shiv Kaushik; Srinivas Chennupaty; Stephan J. Jourdan; Steve H. Gunther; Thomas A. Piazza; Ted Burton

Haswell, Intels fourth-generation core processor architecture, delivers a range of client parts, a converged core for the client and server, and technologies used across many products. It uses an optimized version of Intel 22-nm process technology. Haswell provides enhancements in power-performance efficiency, power management, form factor and cost, core and uncore microarchitecture, and the cores instruction set.

Archive | 2015

Method, apparatus, and system for speculative abort control mechanisms

Martin G. Dixon; Ravi Rajwar; Konrad K. Lai; Robert S. Chappell; Rajesh S. Parthasarathy; Alexandre J. Farcy; Ilhyun Kim; Prakash Math; Matthew C. Merten; Vijaykumar B. Kadgi

Archive | 2012

METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL INSTRUCTIONS

Ravi Rajwar; Martin G. Dixon; Konrad K. Lai; Robert S. Chappell; Bret L. Toll

Archive | 2012

Hybrid cache state and filter tracking of memory operations during a transaction

Robert S. Chappell; Ravi Rajwar; Zhongying Zhang; Jason Bessette

Archive | 2013

Method and apparatus for store durability and ordering in a persistent memory architecture

Subramanya R. Dulloor; Sanjay Kumar; Rajesh M. Sankaran; Gilbert Neiger; Richard Uhlig; Robert S. Chappell; Joseph Nuzman; Kai Cheng; Sailesh Kottapalli; Yen-Cheng Liu; Mohan J. Kumar; Raj K. Ramanujan; Glenn J. Hinton

Archive | 2009

CACHE MEMORY POWER REDUCTION TECHNIQUES

Zhen Fang; Meenakshisundara R. Chinthamani; Li Zhao; Milind B. Kamble; Ravishankar Iyer; Seung Eun Lee; Robert S. Chappell; Ryan L. Carlson

Archive | 2013

APPARATUS AND METHOD FOR A MULTIPLE PAGE SIZE TRANSLATION LOOKASIDE BUFFER (TLB)

Shlomo Raikin; Oren Hamama; Robert S. Chappell; Camron B. Rust; Han S. Luu; Leslie A. Ong; Gur Hildesheim

Archive | 2013

Concurrent Control For A Page Miss Handler

Gur Hildesheim; Chang Kian Tan; Robert S. Chappell; Rohit Bhatia

Archive | 2012

Memory Renaming Mechanism in Microarchitecture

Morris Marden; Vijaykumar Vijay Kadgi; James D. Hadley; Matthew C. Merten; Grace C. Lee; Joseph A. Mcmahon; Robert S. Chappell; Laura A. Knauth; Fariborz Tabesh

Archive | 2014

Instruction and logic for a cache prefetcher and dataless fill buffer

Stanislav Shwartsman; Robert S. Chappell; Ronak Singhal; Ryan L. Carlson; Raanan Sade; Omar M. Shaikh; Liron Zur; Yiftach Gilad

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Martin G. Dixon

Intel

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Ravi Rajwar

Portland State University

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Gur Hildesheim

Intel

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Ho-Seop Kim

Intel

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Konrad K. Lai

Intel

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Matthew C. Merten

Intel

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Rohit Bhatia

Intel

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Shlomo Raikin

Intel

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Alexandre J. Farcy

Intel

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Bret L. Toll

Intel

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