Roberto Cappelletti

A power line FSK transceiver with reduced power consumption

A versatile low-power half-duplex FSK transceiver for power line communication network applications is presented. The proposed power-line modem (PLM) satisfies the requirement of several protocols for power-line communications. The device operation is fully controlled and programmed through an internal 24 bit register. It operates from a single 9 V supply (5 V is possible if no power delivery is required). During transmission, the PLM is able to deliver 1 W on 16 /spl Omega/, while during reception it dissipates only 3.5 mA. The PLM is realized in a 0.6 /spl mu/m BCD technology.

LLR- based Bit- loading Algorithm and its Applications to HomePlug AV over OPERA Power- line Channels with Impulsive Noise

In this paper the higher data rate technology of HomePlug, called HomePlug AV, is tested over the power-line channel models proposed by the OPERA project coupled with the Middleton Class A impulsive noise model. In particular the DLC bit-loading algorithm is developed and the performance is analyzed in terms of throughput when different scenarios are considered. To better exploit the error correction capabilities of the turbo code, this bitloading algorithm attempts to maximize the throughput while guaranteeing a target BER over a set of sub-carriers using a new metric based on the LLRs. Simulations show that the effect of the impulsive noise can be reduced by inserting a clipping module before the OFDM demodulator, thus guaranteeing very promising throughputs even in the worst scenarios.