Roberto Muscedere

Efficient techniques for binary-to-multidigit multidimensional logarithmic number system conversion using range-addressable look-up tables

The multidimensional logarithmic number system (MDLNS), which has similar properties to the classical logarithmic number system (LNS), provides more degrees of freedom than the LNS by virtue of having two, or more, orthogonal bases and has the ability to use multiple MDLNS components, or digits. Unlike the LNS, there is no monotonic relationship between standard binary representations and MDLNS representations. Using look-up tables (LUTs) to perform the mapping function can be unrealistic for hardware implementations when large binary ranges or multiple digits are used. This work proposes a novel range-addressable technique for using look-up tables that allows efficient conversion from binary-to-single or multidigit MDLNS with varying accuracies, depending on the selected implementation.

Efficient hardware implementation of the hyperbolic tangent sigmoid function

Efficient implementation of the activation function is important in the hardware design of artificial neural networks. Sigmoid, and hyperbolic tangent sigmoid functions are the most widely used activation functions for this purpose. In this paper, we present a simple and efficient architecture for digital hardware implementation of the hyperbolic tangent sigmoid function. The proposed method employs a piecewise linear approximation as a foundation, and further improves the results using a lookup table. Our design proves to be more efficient considering area × delay as a performance metric when compared to similar proposals. VLSI implementation of the proposed design using a 0.18µm CMOS process is also presented, which shows a 35% improvement over similar recently published architectures.

High Speed VLSI Implementation of the Hyperbolic Tangent Sigmoid Function

The hyperbolic tangent function is commonly used as the activation function in artificial neural networks. In this work two different hardware implementations for the hyperbolic tangent function are proposed. Both methods are based on the approximation of the function rather than calculating it, since it has exponential nature. The first method uses a lookup table to approximate the function, while the second method reduces the size of the table by using range addressable decoding as opposed to the classic decoding scheme. Hardware synthesis results show the proposed methods perform significantly faster, and use less area compared to other similar methods with the same amount of error.

A Delay Generation Technique for Narrow Time Interval Measurement

A new architecture for the on-chip measurement of short-time intervals is proposed in this paper. The measurement method is similar to a typical low-voltage measurement setup where the input signals are first amplified and then measured to relax the dynamic range of the succeeding analog-to-digital converter. In the proposed method, narrow time intervals are first amplified by a time amplifier (TAMP) and then measured by a time-to-digital converter. A delay-locked-loop (DLL) circuit is utilized to design a feedback time amplifier in which the gain is readily programmed by input data to any integer value within a range specified by the number of delay cells in the DLL. The TAMPs gain remains rather unchanged under process and temperature variations due to the inherent negative feedback of the DLL system. The circuit is implemented using complementary metal--oxide semiconductor (CMOS) 0.18- mum technology occupying less than 0.63 mm2 of the silicon area. The simulation results show that the proposed scheme can successfully be employed to measure time intervals in the range of a few tens of picoseconds with acceptable accuracy.

On the use of hash functions for defect detection in textures for in-camera web inspection systems

Hash functions are one way functions which are used in cryptography to ensure integrity of files by creating a binary signature specific to that file. A family of special hash functions are developed, which are simple enough to fit into a small FPGA and can generate one dimensional signatures of repeating texture images. While these hash functions are sensitive enough to detect small changes and defects in texture, they are immune to change in illumination and contrast. Analyses of these signatures and determination of the parameters of the hash functions are presented.

A low-power two-digit multi-dimensional logarithmic number system filterbank architecture for a digital hearing aid

This paper addresses the implementation of a filterbank for digital hearing aids using a multi-dimensional logarithmic number system (MDLNS). The MDLNS, which has similar properties to the classical logarithmic number system (LNS), provides more degrees of freedom than the LNS by virtue of having two, or more, orthogonal bases and the ability to use multiple MDLNS components or digits. The logarithmic properties of the MDLNS also allow for reduced complexity multiplication and large dynamic range, and a multiple-digit MDLNS provides a considerable reduction in hardware complexity compared to a conventional LNS approach. We discuss an improved design for a two-digit 2D MDLNS filterbank implementation which reduces power and area by over two times compared to the original design.

An In-Camera Data Stream Processing System for Defect Detection in Web Inspection Tasks

One of the aims of industrial machine vision is to develop computer and electronic systems to replace human vision in quality control of industrial production. Traditionally these systems consist of a line scan camera, host computer, frame grabber and one or more dedicated processing boards. In this paper we discuss the development of a new integrated design environment, developed for real-time defect detection, that eliminates the need for an external frame grabber and other associated host computer peripheral systems. The processing board contains a reconfigurable field programmable gate array FPGA inside a DALSA CCD camera. The FPGA is directly connected to the video data-stream and outputs data to a low bandwidth output bus. The system is targeted for web inspection but has the potential for broader application areas. We describe and show test results of the in-camera prototype system board and discuss some of the algorithms currently simulated and implemented for web inspection applications.

A 2-digit DBNS filter architecture

We have previously reported on a novel number representation using 2 bases which we refer to as the double-base number system (DBNS). Our preferred implementation uses the relatively prime bases {2,3}. If we allow the exponents of the bases to be arbitrarily large signed integers, then we can represent any real number to any arbitrary precision by a single digit DBNS representation. By representing the digit position by the exponent values, we generate a logarithmic-like representation which we can manipulate using an index calculus. A multiplier accumulator architecture for a FIR filter application has been reported which uses a half-index domain to remove the problem of addition within the index calculus. In this paper we show that using a 2-digit DBNS representation for both the input data and the filter coefficients can result in substantial hardware savings compared to both the single-digit a DBNS approach and an equivalent binary implementation of a general multiplier accumulator. In the paper we discuss the filter architecture, techniques for converting between binary and the 2-digit DBNS representations, and also the design technique used to generate the 2-digit DBNS FIR filter coefficients.

Defect detection in web inspection using fuzzy fusion of texture features

This paper describes a novel approach for real-time defect detection targeted to web inspection systems using real-time processing of raster scanned images. Our new method utilizes a fuzzy fusion of texture features to detect image rows that contain defects, without requiring access to the two dimensional frame data. The method is suitable for in-camera processing where an FPGA is directly connected to the digitized video stream. This method is successfully implemented in the limited resources of one FPGA without the use of a frame-grabber.

Efficient conversion from binary to multi-digit multi-dimensional logarithmic number systems using arrays of range addressable look-up tables

The multi-dimensional logarithmic number system (MDLNS), with similar properties to the logarithmic number system (LNS), provides more degrees of freedom than the LNS by virtue of having two orthogonal bases and the ability to use multiple digits. Unlike the LNS, there is no direct functional relationship between binary/floating point representation and the MDLNS representation. Traditionally look-up tables (LUTs) were used to move from the binary domain to the MDLNS domain. This method can be unrealistic for hardware implementation when large binary ranges or multiple digits are used. This paper introduces a range addressable technique for table look-up arrays that allows efficient conversion from binary to single or multi-digit MDLNS.