Roberto S. Maurino

A 200-MHz IF 11-bit fourth-order bandpass /spl Delta//spl Sigma/ ADC in SiGe

This paper demonstrates the design of an integrated fourth-order bandpass sigma-delta converter, which is capable of digitizing a 200-kHz band at 200 MHz with 11-bit accuracy. The converter has been successfully fabricated in a 50-GHz SiGe bipolar technology, and the modulator consumes 21 mA at 3 V. The converter is aimed at the digitization of wireless signals at a high first intermediate frequency with a wide dynamic range.

Quadrature /spl Sigma//spl Delta/ modulators with a dynamic element matching scheme

This paper presents a new topology of a multibit quadrature bandpass sigma-delta modulator which employs a simple dynamic element matching (DEM) technique in order to reduce the effects of path mismatch, namely aliasing in the signal band of the mirror images of the signal and of the quantization noise. The DEM scheme results in a reduction of the aliasing of the quantization noise mirror image while it reduces the input signal mirror image alias problem to a self-image problem. It is shown that the self-image can be completely removed in switched-capacitor implementations by using the same capacitors to sample the input and the reference of the feedback digital-analog converters (DACs). Moreover, a simple method for extending low-pass mismatch noise shaping techniques to the complex bandpass case is proposed for the case of multibit feedback DACs.

Multibit quadrature sigma-delta modulator with DEM scheme

A simple dynamic element matching (DEM) scheme for sampled data systems is presented. The scheme is suitable for switch-capacitor (SC) or switch-current circuits. The DEM scheme eliminates the mirror spectral image around +/-F/sub s//4, where F/sub s/ is the sampling frequency, while generally introducing a more benign self-image. The scheme is suitable for quadrature SC band-pass(BP) /spl Sigma//spl Delta/ modulators with a centre frequency at F/sub s//4 or

A 10mW 81dB cascaded multibit quadrature /spl Sigma//spl Delta/ ADC with a dynamic element matching scheme

F/sub s//4, where it can minimize the quantization noise mirror image and where the signal mirror image can be suppressed. Furthermore, a quadrature mismatch noise shaping method that can be used with this DEM scheme is introduced.

Subtractive dithering technique for delta-sigma modulator

A multibit 2-0 cascaded quadrature /spl Sigma//spl Delta/ modulator is presented which attains 81 dB dynamic range in a 200kHz bandwidth at an IF of 10MHz. A simple dynamic element matching (DEM) scheme minimizes the mirror in-band aliases caused by mismatch between the I and Q channel. The integral nonlinearity (INL) errors from the multibit feedback DAC are noise-shaped by a quadrature variant of the data weighted averaging algorithm (DWA). Clocked at 13.1 MHz, the ADC consumes 10mW from a 2.1 V supply.

5.7 A 19nV/√Hz-noise 2µV-offset 75µA low-drift capacitive-gain amplifier with switched-capacitor ADC driving capability

This paper presents a novel subtractive dithering technique used in delta-sigma modulators which improves the spectral integrity of the modulators while minimizing the tradeoffs due to the use of dither. Dithering is commonly used in delta-sigma modulators to eliminate idle tones. The proposed technique adds dither at input of the quantizer and subtracts the dither in the analog domain at input of the modulator and in the digital domain at the output of modulator. The simulation results prove that when compared to the conventional dithering technique, this new subtractive dithering technique achieves the idle tone-free result but does not have the traditional drawbacks such as increased integrator output swing and in-band noise floor degradation.

PROGRAMMABLE GAIN AMPLIFIER WITH AMPLIFIER COMMON MODE SAMPLING SYSTEM

This paper describes a capacitive programmable-gain amplifier (CGA) with amplifier common-mode sampling (CMS) and switched-capacitor driving capability, compatible with many conventional switched-capacitor ADC inputs (SCAI) such as delta-sigma modulators or SAR ADCs. CGAs are popular for their low power, low noise and high precision [1,2]. The capacitive gain network is highly linear, does not dissipate static power and can be noiseless. Capacitors have excellent matching and temperature drift, which has a positive impact on offset/gain errors and their drift. They also offer a high input impedance at low frequencies and rail-to-rail operation, which makes them very suitable to interface with different types of sensors.