Robin R.-B. Sheen

A low-power adder operating on effective dynamic data ranges

To design a power-efficient digital signal processor, this study develops a fundamental arithmetic unit of a low-power adder that operates on effective dynamic data ranges. Before performing an addition operation, the effective dynamic ranges of two input data are determined. Based on a larger effective dynamic range, only selected functional blocks of the adder are activated to generate the desired result while the input bits of the unused functional blocks remain in their previous states. The added result is then recovered to match the required word length. Using this approach to reduce switching operations of noneffective bits allows input data in 2s complement and sign magnitude representations to have similar switching activities. This investigation thus proposes a 2s complement adder with two master-stage and slave-stage flip-flops, a dynamic-range determination unit and a sign-extension unit, owing to the easy implementation of addition and subtraction in such a system. Furthermore, this adder has a minimum number of transistors addressed by carry-in bits and thus is designed to reduce the power consumption of its unused functional blocks. The dynamic range and sign-extension units are explored in detail to minimize their circuit area and power consumption. Experimental results demonstrate that the proposed 32-bit adder can reduce power dissipation of conventional low-power adders for practical multimedia applications. Besides the ripple adder, the proposed approach can be utilized in other adder cells, such as carry lookahead and carry-select adders, to compromise complexity, speed and power consumption for application-specific integrated circuits and digital signal processors.

A dual-band RF front-end for WCDMA and GPS applications

In this work, a dual-band radio frequency (RF) front-end, which can be operated for wideband code division multiple access (WCDMA) and Global Positioning System (GPS), is developed. This RF front-end includes two differential low noise amplifiers, double-balanced mixers of I and Q channels and a multiphase voltage-controlled oscillator (VCO). The front-end architecture without external components is implemented by the low intermediate frequency (IF) technique which is very suitably for circuit integration. As compared to the other RF front-ends receiving multi-frequency bands, the proposed front-end utilizes two low noise amplifiers, shared mixers and multiphase VCO to reduce the hardware complexity. In addition, this architecture is easily scaled to receive more than two frequency bands. Here, a multiphase VCO consisting of a phase-setting unit and range-programmable VCO is utilized to generate two frequency bands having four phases. The frequency band is determined by the number of paralleled inverter rings in the proposed range-programmable VCO. Compared to conventional oscillators, the proposed multiphase VCO can improve phase noise and phase accuracy due to the closed-loop trigger between the phase-setting unit and the range-programmable VCO. By using the TSMC IP6M 0.18 /spl mu/m CMOS technology, the proposed dual-band RF front-end was designed at a supply voltage of 1.8 V to have a gain of 30 dB for IF at 2 MHz, IIP3 of -30 dBm and a noise figure of 5 dB.

Power consumption of a 2's complement adder minimized by effective dynamic data ranges

Typically, twos complement is chosen to represent numbers since arithmetic operations of addition and subtraction are easy to perform. However, due to sign extension, an arithmetic operation for small dynamic data ranges may require switching power in the entire word length. Herein, we develop a twos complement adder with the dynamic-range determination and sign-extension units to reduce power consumption. According to the actual data range by minimizing sign-extension bits, only partial functional blocks of an adder are active to generate a final result of which sign bit is then extended to match the original word length. Experimental results demonstrate that our 32-bit carry-lookahead adder has 22.9% power reduction than the conventional one while dynamic ranges of input data are the Gaussian distribution with a mean of 16 bits and a standard deviation of 8 bits.

A 3.3 V 600 MHz-1.30 GHz CMOS phase-locked loop for clock synchronization of optical chip-to-chip interconnects

A high-speed phase-locked loop for clock synchronization of optical chip-to-chip interconnects has been developed. It consists of a photo-diode, an amplifier, a phase detector, a charge pump, a loop filter, and a voltage control oscillator. In order to make our phase-locked loop operate in optical interconnects efficiently, we apply an improved fully integrated CMOS photo-detector, and propose a new phase-locked loop with a high-speed three-state phase detector and a wide-range voltage control resistor. The proposed phase-locked loop has been implemented by using the UMC 0.5 /spl mu/m CMOS technology with a die size of 300 /spl mu/m/spl times/400 /spl mu/m. The HSPICE simulation results show that the optical signals from 1.2 Gb/s (600 MHz) to 2.6 Gb/s (1.3 GHz) can be locked at a supply voltage of 3.3 V. The jitter of proposed phase-locked loop at 1 GHz is less than 15 ps. Its power consumption is around 150 mW. Therefore, our phase-locked can be widely used in high-frequency and low-power optical chip-to-chip interconnect systems.

A high-performance CMOS multiphase voltage-controlled oscillator for communication systems

A multiphase oscillator employing phase-setting and oscillation-generation units was developed for modern communication systems. The phase-setting unit includes multiple cascading phase-shifting cells the number of which determines output signal phase differences. The oscillation-generation unit consists of multiple oscillators to trigger the phase-setting unit. This configuration ensures that the proposed multiphase oscillator has good oscillation quality and high phase accuracy. In addition, a voltage-controlled ring oscillator capable of generating two oscillation signals with a phase difference of 180/spl deg/ is designed. It not only decreases the settling time of the multiphase oscillation system, but also reduces power dissipation due to its simplicity. By using TSMC 1P6M 0.18 /spl mu/m CMOS technology, the proposed multiphase voltage-controlled oscillator (VCO) yields oscillation signals ranging from 2.37 GHz to 2.53 GHz at a supply voltage of 1.8 V. There are 8 oscillation signals with phase differences of 45/spl deg/, 90/spl deg/, 135/spl deg/, 180/spl deg/, 225/spl deg/, 270/spl deg/, 315/spl deg/ and 360/spl deg/. Power dissipation is around 4.21 mW to 4.88 mW.

A wide-range phase-locked loop using a range-programmable voltage-controlled oscillator

A wide-range phase-locked loop incorporating a range-programmable voltage-controlled oscillator was developed for clock generation without an additional frequency synthesizer. Breaking down the original inverter into several smaller ones and re-combining them paralleled could extend the output frequency range effectively, and operate more efficiently. Using TSMC 1P3M 0.6 /spl mu/m CMOS technology, the proposed phase-locked loop at a supply voltage of 3.3 V was measured with output signals of 184 MHz to 1.04 GHz at power dissipation ranging from 8.24 mW to 32.13 mW.

A CMOS PLL-based frequency synthesizer for wireless communication systems at 0.9, 1.8, 1.9 and 2.4 GHz

In this paper, a phase-locked loop (PLL)-based frequency synthesizer was developed for wireless communication applications at 900 MHz, 1800 MHz, 1900 MHz and 2.4 GHz. In order to generate wide-range oscillation signals in the desired frequency bands, a range-programmable voltage-controlled oscillator (RP-VCO) consisting of several controllable inverter rings in parallel was designed. By adjusting the ratios of programmable dividers, and selecting the number of paralleled inverter rings of the RP-VCO, the desired frequency can be generated as demanded by the application system. Instead of using several synthesizers for different frequency bands, only a synthesizer proposed herein can generate these frequency bands in a cost-effective way. By using the TSMC 1P4M 0.35 /spl mu/m CMOS technology, the proposed PLL-based frequency synthesizer could yield oscillation signals ranging from 822 MHz to 967 MHz, from 1752 MHz to 1874 MHz, from 1849 MHz to 1933 MHz and from 2356 MHz to 2503 MHz at a supply voltage of 3.3 V. Power dissipation is proportional to the output frequency with 11.6 mW to 35.3 mW. Therefore, the proposed frequency synthesizer could be widely used in various integrated communication systems, providing different oscillation signals in cost-effective and power-efficient manners.

A low-power and high-frequency CMOS transceiver for chip-to-chip interconnection

In this paper, we developed a low-power and high-frequency transceiver by using the TSMC 0.35 um CMOS single-poly-four-metal technology. The proposed transceiver includes a photo-detector and a laser diode driver where the photodiode and laser diode can be packaged by using the flip-chip connections. The proposed photo-detector indirectly senses the photo current and uses a bias voltage to control a current source and to provide an adequate reversed bias voltage of the photodiode. The laser diode driver is implemented by using a current mirror and two gate-control transistors. A prototype chip of two 2/spl times/2 receivers and two 2/spl times/2 transmitters are implemented with a die size of 2.4 mm/spl times/2.4 mm where the CMOS photodiodes with ring-type electrodes are designed. At a supply voltage of 3.3 V, the proposed photo-detector and laser diode driver can be operated at a clock frequency of 1 GHz with power dissipation of 3.8 mW and 5.0 mW, respectively, where the photodiode provides 100 /spl mu/A and the laser diode has a threshold current of 0.6 mA for a light wavelength of 850 nm. Therefore, the proposed transceiver can be widely used in low-power and high-frequency chip-to-chip interconnection systems.

Transimpedance Limit Exploration and Inductor-Less Bandwidth Extension for Designing Wideband Amplifiers

This brief studies the transimpedance of the regulated cascode (RGC) structure and develops a multilevel active feedback (MLAF) structure to build an inductorless CMOS differential transimpedance amplifier (TIA). The proposed TIA consists of an input stage, a single-to-differential circuit, a gain stage, and an output buffer. The input stage adopts the RGC structure of which transimpedance is theoretically characterized and numerically analyzed to determine design parameters. In the gain stage, the MLAF structure in a hierarchical feedback topology is investigated to increase the bandwidth without inductor peaking. The proposed differential TIA was simulated at the 180-nm, 90-nm, and 28-nm CMOS technologies to verify our design methodology. In addition, the TSMC 180-nm CMOS technology was employed to implement the proposed TIA with a core size of 0.05 mm2, a bandwidth of 7.2 GHz, and a differential transimpedance gain of 1.8 kΩ. Comparing with conventional TIAs, the proposed TIA exhibits the least hardware cost and fairly good performance for applications of 10-Gbit/s optical communications.

A 1.3 V 1.04 GHz-1.30 GHz CMOS phase-locked loop

A low-voltage and high-frequency phase-locked loop for clock generation has been developed. It consists of a phase detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. In order to make our phase-locked loop operate at a low supply voltage, a new voltage-control resistor is designed to overcome a transistors threshold voltage for a wide-range control in the voltage-control oscillator. With a high-frequency operation, the adequate loop gain of the phase-locked loop has been effectively addressed to achieve a stable locking process. The low-power and high-frequency circuit design schemes are also presented. The proposed phase-locked loop has been implemented by using the UMC 0.5 u double-poly double-metal CMOS technology with a die size of 200 /spl mu/m/spl times/400 /spl mu/m. The HSPICE simulation results show that the clocks from 1.04 GHz to 1.30 GHz can be generated at a supply voltage of 1.3 V. The jitter of the proposed phase-locked loop at 1.2 GHz is below 4 degrees. Its power consumption is around 5.3 mW. Therefore, our phase-locked loop can be widely used in low-power and high-frequency applications.