Rodney R. Rozman

A multilevel-cell 32 Mb flash memory

A flash memory with multilevel cell significantly reduces the memory per-bit cost. A 32 Mb multilevel-cell (MLC) flash memory storing two bits of data per cell achieves 32 Mb memory storage capacity using 16 M flash memory cells. This 32 Mb flash memory on a 0.6 /spl mu/m process has a 2.0/spl times/1.8 /spl mu/m/sup 2/ flash cell. In MLC operation, the logical flash memory cell achieves two bits per cell using four possible states, defined by four flash cell threshold voltage ranges. The relationship between the threshold voltage ranges stored in the flash memory cell and the corresponding logic levels is shown in this paper, which also shows a plot of the four threshold voltage distributions, each with a separation range.

A 3.3 V 16 Mb flash memory with advanced write automation

The design of this flash memory is governed by the following considerations. Use of flash memory to store both data and code requires fast write with interruptible erase. Portable systems operate at 3.3 V to optimize battery life, while the desktop remains primarily a 5 V platform. This 16 Mb flash memory on a 0.6 /spl mu/m CMOS process operates with either 3.3 or 5 V supply. In the 3.3 V mode, a word line boost circuit is enabled, the input buffer trip points are modified, and the read path circuits are reconfigured for optimum performance. This memory uses the host computer 12 V supply to minimize flash media cost and maximize flash media performance. The device contains an advanced user interface that allows the host to queue up to three commands for execution by the write state machine, designed to allow erase to be interrupted so a program operation can be executed. Two 256B page buffers improve write performance and reduce host overhead. Wafer yields are improved by including redundant row pairs and columns.<<ETX>>

A 3.3V 50MHz synchronous 16Mb flash memory

A 3.3 V 50 MHz synchronous 16 Mb flash memory serves applications where zero-wait-state direct execution is essential in removing the performance bottleneck attributed to slow memory in performance (/spl ges/25 MHz) systems. This 16 Mb flash chip supports continuous burst cycles for code execution, eliminating costly code shadowing from slow nonvolatile memory to DRAM, resulting in improved system performance and lower cost. Architecture and circuit innovations give 20 ns continuous burst and a maximum data transfer rate of 100 MB/s, resulting in a greater than 3/spl times/ performance improvement over previous 16 Mb devices.